/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 222 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 245 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 385 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 386 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 389 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 390 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 484 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 485 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 488 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 489 { ISD::UREM, MVT::v4i32, 2 [all...] |
H A D | X86ISelLowering.cpp | 917 addRegisterClass(MVT::v4i32, Subtarget.hasVLX() ? &X86::VR128XRegClass 935 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 937 setOperationAction(ISD::MULHU, MVT::v4i32, Custom); 938 setOperationAction(ISD::MULHS, MVT::v4i32, Custom); 952 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { 967 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom); 971 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 974 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { 987 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) { 1010 setOperationAction(ISD::SELECT, MVT::v4i32, Custo [all...] |
H A D | X86ISelDAGToDAG.cpp | 4319 VPTESTM_CASE(v4i32, DZ128##SUFFIX) \ 5739 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32) 5745 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64) 5747 else if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 64) 5766 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32) 5770 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64) 5772 else if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 64) 5833 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32) 5839 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64) 5841 else if (IndexVT == MVT::v4i32 [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 459 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0}, 460 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0}, 461 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0}, 462 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0}, 496 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i16, 0}, 497 {ISD::TRUNCATE, MVT::v4i32, MVT::v4i8, 0}, 528 { ISD::ADD, MVT::v4i32, MVT::v4i16, 0 }, 531 { ISD::SUB, MVT::v4i32, MVT::v4i16, 0 }, 534 { ISD::MUL, MVT::v4i32, MVT::v4i16, 0 }, 537 { ISD::SHL, MVT::v4i32, MV 1605 {ISD::ADD, MVT::v4i32, 1}, member in class:MVT [all...] |
H A D | ARMISelLowering.cpp | 233 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 257 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 }; 407 // It is legal to extload from v4i8 to v4i16 or v4i32. 409 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal); 410 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal); 412 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16. 415 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal); 420 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal); 421 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal); 806 addQRTypeForNEON(MVT::v4i32); [all...] |
H A D | ARMISelDAGToDAG.cpp | 1800 (CanChangeType || LoadedVT == MVT::v4i32 || 2110 case MVT::v4i32: OpcodeIndex = 2; break; 2255 case MVT::v4i32: OpcodeIndex = 2; break; 2423 case MVT::v4i32: OpcodeIndex = 1; break; 2959 case MVT::v4i32: OpcodeIndex = 2; break; 4063 case MVT::v4i32: Opc = ARM::VZIPq32; break; 4086 case MVT::v4i32: Opc = ARM::VUZPq32; break; 4108 case MVT::v4i32: Opc = ARM::VTRNq32; break;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/ |
H A D | WebAssemblyTypeUtilities.cpp | 70 .Case("v4i32", MVT::v4i32) 139 case MVT::v4i32:
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetTransformInfo.cpp | 234 MVT::v8i16, MVT::v2i32, MVT::v4i32}; 245 MVT::v8i16, MVT::v2i32, MVT::v4i32, 258 MVT::v8i16, MVT::v2i32, MVT::v4i32, 621 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 622 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 646 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 647 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 663 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 666 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 704 { ISD::FP_TO_SINT, MVT::v4i32, MV 1631 {ISD::ADD, MVT::v4i32, 1}, member in class:MVT [all...] |
H A D | AArch64ISelDAGToDAG.cpp | 676 case MVT::v4i32: 705 case MVT::v4i32: 716 case MVT::v4i32: 3579 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3606 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3633 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3660 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3687 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3714 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { 3741 } else if (VT == MVT::v4i32 || V [all...] |
H A D | AArch64ISelLowering.cpp | 274 addQRTypeForNEON(MVT::v4i32); 993 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32); 994 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32); 1006 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16 1007 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom); 1008 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom); 1018 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i16, MVT::v4i32); 1019 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i16, MVT::v4i32); 1033 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 1038 MVT::v16i8, MVT::v8i16, MVT::v4i32, MV [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
H A D | MachineValueType.h | 97 v4i32 = 48, // 4 x i32 392 SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 || 559 case v4i32: 750 case v4i32: 915 case v4i32: 1173 if (NumElements == 4) return MVT::v4i32;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 64 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); 79 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, 134 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) 166 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) 170 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, 175 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, 181 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) 186 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, 194 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, 201 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MV [all...] |
H A D | WebAssemblyFastISel.cpp | 140 case MVT::v4i32: 691 case MVT::v4i32: 801 case MVT::v4i32: 1358 case MVT::v4i32:
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H A D | WebAssemblyAsmPrinter.cpp | 64 MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 715 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) { 768 // We promote all non-typed operations to v4i32. 770 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 772 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 774 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 776 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 778 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 781 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); 783 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 831 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expan [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 36 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); 46 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); 69 setLoadExtAction(ISD::EXTLOAD, MVT::v4i32, MVT::v4i1, Expand); 70 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); 71 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); 76 setOperationAction(ISD::STORE, MVT::v4i32, Custom); 83 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom); 88 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); 95 setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand); 119 setOperationAction(ISD::SETCC, MVT::v4i32, Expan [all...] |
H A D | AMDGPUISelLowering.cpp | 76 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); 94 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32); 100 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32); 196 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32); 214 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32); 220 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32); 264 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Expand); 324 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 335 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); 415 MVT::v2i32, MVT::v3i32, MVT::v4i32, MV [all...] |
H A D | SIISelLowering.cpp | 98 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass); 145 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); 154 setOperationAction(ISD::STORE, MVT::v4i32, Custom); 163 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand); 168 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand); 205 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Expand); 277 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32. 280 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32); 283 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32); 286 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.cpp | 1046 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then 1085 ViaVecTy = MVT::v4i32; 1153 CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0)); 1254 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, 1258 Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
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H A D | MipsSEInstrInfo.cpp | 277 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || 355 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
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H A D | MipsSEISelLowering.cpp | 120 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); 355 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) { 1397 ViaVecTy = MVT::v4i32; 1435 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's. 1436 ViaVecTy = MVT::v4i32; 1485 DAG.getBuildVector(MVT::v4i32, DL, 1886 // an equivalent v4i32. 2497 ViaVecTy = MVT::v4i32;
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/netbsd-current/external/apache2/llvm/dist/clang/lib/Headers/ |
H A D | msa.h | 22 typedef int v4i32 __attribute__((vector_size(16), aligned(16))); typedef
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/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/mips/ |
H A D | msa.h | 39 typedef int v4i32 __attribute__ ((vector_size(16), aligned(16))); typedef
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/netbsd-current/external/gpl3/gcc/dist/gcc/config/mips/ |
H A D | msa.h | 39 typedef int v4i32 __attribute__ ((vector_size(16), aligned(16))); typedef
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | ValueTypes.cpp | 268 case MVT::v4i32:
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