Searched refs:v4f32 (Results 1 - 25 of 31) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp211 { ISD::FDIV, MVT::v4f32, 35 }, // divps
226 { ISD::FMUL, MVT::v4f32, 2 }, // mulps
228 { ISD::FDIV, MVT::v4f32, 39 }, // divps
800 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
837 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
852 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
857 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
862 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
865 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/
931 { ISD::FDIV, MVT::v4f32, 3
[all...]
H A DX86ISelLowering.cpp801 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32,
885 addRegisterClass(MVT::v4f32, Subtarget.hasVLX() ? &X86::VR128XRegClass
888 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
889 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
890 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Custom);
891 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
893 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
895 setOperationAction(ISD::SELECT, MVT::v4f32, Custo
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp484 {ISD::FP_EXTEND, MVT::v4f32, MVT::v4f16, 1},
512 {ISD::FP_ROUND, MVT::v4f32, MVT::v4f16, 1},
560 {ISD::FP_EXTEND, MVT::v4f32, 4}};
603 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
604 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
612 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
613 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
614 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
615 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
616 { ISD::SINT_TO_FP, MVT::v4f32, MV
[all...]
H A DARMISelLowering.cpp324 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
802 addQRTypeForNEON(MVT::v4f32);
859 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
860 // supported for v4f32.
861 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
862 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
863 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
864 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
865 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
866 setOperationAction(ISD::FLOG2, MVT::v4f32, Expan
[all...]
H A DARMISelDAGToDAG.cpp1801 LoadedVT == MVT::v4f32) &&
2109 case MVT::v4f32:
2254 case MVT::v4f32:
2422 case MVT::v4f32:
2958 case MVT::v4f32:
3116 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32,
3128 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32,
4062 case MVT::v4f32:
4085 case MVT::v4f32:
4107 case MVT::v4f32
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp663 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
666 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
677 // Complex: to v4f32
678 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
679 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
680 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
681 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
704 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
707 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
718 // Complex, from v4f32
[all...]
H A DAArch64ISelDAGToDAG.cpp2034 (VT != MVT::v4f32 || NarrowVT != MVT::v4f16))
3579 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3606 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3633 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3660 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3687 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3714 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3741 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3768 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
3795 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) {
[all...]
H A DAArch64ISelLowering.cpp270 addQRTypeForNEON(MVT::v4f32);
632 // promote v4f16 to v4f32 when that is known to be safe.
637 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
638 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
639 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
640 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
1006 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
1047 MVT::v8f16, MVT::v4f32, MVT::v2f64 }) {
1094 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
1195 {MVT::v4f16, MVT::v8f16, MVT::v2f32, MVT::v4f32, MV
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp141 case MVT::v4f32:
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h147 v4f32 = 90, // 4 x f32
395 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
623 case v4f32:
754 case v4f32:
920 case v4f32:
1225 if (NumElements == 4) return MVT::v4f32;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp109 addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
341 // as such. In particular, we can do these for v4f32 even though there
428 setOperationAction(ISD::FP_TO_SINT, MVT::v4f32, Legal);
430 setOperationAction(ISD::FP_TO_UINT, MVT::v4f32, Legal);
432 setOperationAction(ISD::SINT_TO_FP, MVT::v4f32, Legal);
434 setOperationAction(ISD::UINT_TO_FP, MVT::v4f32, Legal);
437 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4f32, Legal);
439 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4f32, Legal);
441 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4f32, Legal);
443 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4f32, Lega
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp866 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
867 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
868 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
869 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
881 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
886 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
887 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
890 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
891 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
924 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custo
[all...]
H A DPPCTargetTransformInfo.cpp1131 LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp141 case MVT::v4f32:
699 case MVT::v4f32:
807 case MVT::v4f32:
1360 case MVT::v4f32:
H A DWebAssemblyISelLowering.cpp65 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
79 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
100 for (auto T : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
170 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
175 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
186 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
194 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
212 for (auto T : {MVT::v4f32, MVT::v2f64})
270 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32,
H A DWebAssemblyAsmPrinter.cpp64 MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp75 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
76 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
169 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
176 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
195 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
196 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
253 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
266 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Expand);
325 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
334 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custo
[all...]
H A DR600ISelLowering.cpp35 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass);
184 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
189 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
541 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
1386 // non-constant ptr can't be folded, keeps it as a v4f32 load
/netbsd-current/external/apache2/llvm/dist/clang/lib/Headers/
H A Dmsa.h30 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/mips/
H A Dmsa.h47 typedef float v4f32 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/gpl3/gcc/dist/gcc/config/mips/
H A Dmsa.h47 typedef float v4f32 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp278 TRI->isTypeLegalForClass(*RC, MVT::v4f32))
356 TRI->isTypeLegalForClass(*RC, MVT::v4f32))
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp136 case MVT::v4f32:
440 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
442 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
2296 case MVT::v4f32:
3864 Info.memVT = MVT::v4f32;
4777 case MVT::v4f32:
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DValueTypes.cpp352 case MVT::v4f32:
/netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenTarget.cpp154 case MVT::v4f32: return "MVT::v4f32";

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