Searched refs:v2i64 (Results 1 - 25 of 32) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp233 // v2i64/v4i64 mul is custom lowered as a series of long:
238 { ISD::MUL, MVT::v2i64, 17 },
240 { ISD::ADD, MVT::v2i64, 4 },
241 { ISD::SUB, MVT::v2i64, 4 },
333 { ISD::SRA, MVT::v2i64, 1 },
555 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
559 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
574 { ISD::MUL, MVT::v2i64, 1 },
608 { ISD::SRA, MVT::v2i64, 1 },
641 { ISD::SHL, MVT::v2i64,
[all...]
H A DX86ISelLowering.cpp919 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
936 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
952 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
968 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom);
974 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
995 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
1000 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
1007 // Custom lower v2i64 and v2f64 selects.
1009 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1065 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custo
[all...]
H A DX86ISelDAGToDAG.cpp4320 VPTESTM_CASE(v2i64, QZ128##SUFFIX) \
5751 else if (IndexVT == MVT::v2i64 && NumElts == 4 && EltSize == 32)
5757 else if (IndexVT == MVT::v2i64 && NumElts == 2 && EltSize == 64)
5774 else if (IndexVT == MVT::v2i64 && NumElts == 4 && EltSize == 32)
5778 else if (IndexVT == MVT::v2i64 && NumElts == 2 && EltSize == 64)
5845 else if (IndexVT == MVT::v2i64 && NumElts == 4 && EltSize == 32)
5851 else if (IndexVT == MVT::v2i64 && NumElts == 2 && EltSize == 64)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp71 .Case("v2i64", MVT::v2i64)
140 case MVT::v2i64:
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp573 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
574 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
583 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 3 },
584 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 3 },
585 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 2 },
586 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2 },
729 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 10 },
730 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 2 },
733 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 10 },
734 { ISD::ZERO_EXTEND, MVT::v2i64, MV
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp227 if (LT.second == MVT::v2i64)
246 MVT::v2i64};
259 MVT::v2i64};
664 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
667 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
672 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
675 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
705 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
708 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
710 // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (
[all...]
H A DAArch64ISelDAGToDAG.cpp708 case MVT::v2i64:
719 case MVT::v2i64:
3585 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3612 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3639 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3666 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3693 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3720 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3747 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3774 } else if (VT == MVT::v2i64 || V
[all...]
H A DAArch64SelectionDAGInfo.cpp99 MVT::v2i64,
H A DAArch64ISelLowering.cpp275 addQRTypeForNEON(MVT::v2i64);
1003 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
1004 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
1025 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
1030 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
1034 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
1038 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1063 setOperationAction(ISD::VECREDUCE_ADD, MVT::v2i64, Custom);
1197 MVT::v2i32, MVT::v4i32, MVT::v1i64, MVT::v2i64}) {
1287 setOperationAction(ISD::CTLZ, MVT::v2i64, Custo
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h110 v2i64 = 60, // 2 x i64
393 SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 ||
577 case v2i64:
774 case v2i64:
916 case v2i64:
1187 if (NumElements == 2) return MVT::v2i64;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp66 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
79 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
134 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
166 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
170 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
175 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
181 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
186 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
194 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
201 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
[all...]
H A DWebAssemblyFastISel.cpp142 case MVT::v2i64:
695 case MVT::v2i64:
804 case MVT::v2i64:
1359 case MVT::v2i64:
H A DWebAssemblyAsmPrinter.cpp64 MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp728 // For v2i64, these are only valid with P8Vector. This is corrected after
833 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
834 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
835 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
836 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
879 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
901 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
902 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
903 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
906 setOperationAction(ISD::UDIV, MVT::v2i64, Lega
[all...]
H A DPPCTargetTransformInfo.cpp1133 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp1089 ViaVecTy = MVT::v2i64;
1181 CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1271 Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1318 Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64,
H A DMipsSEISelLowering.cpp121 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
355 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
1380 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1386 if (ResVecTy == MVT::v2i64) {
1434 if (VecTy == MVT::v2i64) {
1435 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1472 if (VecTy == MVT::v2i64) {
1484 ISD::BITCAST, DL, MVT::v2i64,
1495 if (VecTy == MVT::v2i64)
1512 MVT ResEltTy = ResTy == MVT::v2i64
[all...]
H A DMipsSEInstrInfo.cpp280 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
358 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
/netbsd-current/external/apache2/llvm/dist/clang/lib/Headers/
H A Dmsa.h26 typedef long long v2i64 __attribute__((vector_size(16), aligned(16))); typedef
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/mips/
H A Dmsa.h43 typedef long long v2i64 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/gpl3/gcc/dist/gcc/config/mips/
H A Dmsa.h43 typedef long long v2i64 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp108 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
364 if (VT != MVT::v2i64)
407 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
409 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
411 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
413 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
416 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
418 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
420 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
422 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Lega
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp93 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
94 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
213 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
214 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
245 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
246 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);
247 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
248 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
345 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i64, Custom);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DValueTypes.cpp292 case MVT::v2i64:
/netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenTarget.cpp126 case MVT::v2i64: return "MVT::v2i64";

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