Searched refs:v2f64 (Results 1 - 25 of 31) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp213 { ISD::FDIV, MVT::v2f64, 65 }, // divpd
225 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd
230 { ISD::FDIV, MVT::v2f64, 69 }, // divpd
231 { ISD::FADD, MVT::v2f64, 2 }, // addpd
232 { ISD::FSUB, MVT::v2f64, 2 }, // subpd
795 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/
803 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
833 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/
840 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/
851 { ISD::FADD, MVT::v2f64,
[all...]
H A DX86ISelLowering.cpp802 MVT::v2f64, MVT::v4f64, MVT::v8f64 }) {
908 addRegisterClass(MVT::v2f64, Subtarget.hasVLX() ? &X86::VR128XRegClass
948 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
949 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
950 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Custom);
995 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
1007 // Custom lower v2i64 and v2f64 selects.
1008 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1095 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1096 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Lega
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp30 // For the 2nd half of a v2f64, do not fail.
55 if (LocVT == MVT::v2f64 &&
77 // For the 2nd half of a v2f64, do not just fail.
108 if (LocVT == MVT::v2f64 &&
140 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
223 case MVT::v2f64:
H A DARMTargetTransformInfo.cpp558 {ISD::FP_ROUND, MVT::v2f64, 2},
635 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
636 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
638 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
639 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
640 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
641 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
642 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
643 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
645 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64,
[all...]
H A DARMISelLowering.cpp233 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
392 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
400 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
803 addQRTypeForNEON(MVT::v2f64);
821 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
823 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
824 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
825 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
829 setOperationAction(ISD::FREM, MVT::v2f64, Expan
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp664 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
667 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
693 // Complex: to v2f64
694 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
695 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
696 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
697 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
698 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
699 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
705 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64,
[all...]
H A DAArch64ISelDAGToDAG.cpp2033 if ((VT != MVT::v2f64 || NarrowVT != MVT::v2f32) &&
2048 auto Opcode = VT == MVT::v2f64 ? AArch64::FCVTLv4i32 : AArch64::FCVTLv8i16;
3585 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3612 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3639 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3666 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3693 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3720 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3747 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3774 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
[all...]
H A DAArch64ISelLowering.cpp271 addQRTypeForNEON(MVT::v2f64);
1047 MVT::v8f16, MVT::v4f32, MVT::v2f64 }) {
1094 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
1196 MVT::v2f64, MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
1336 MVT::v1f64, MVT::v2f64})
1363 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
6756 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
6777 if (VT == MVT::f64 || VT == MVT::v2f64) {
6778 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
6779 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVe
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp142 case MVT::v2f64:
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h160 v2f64 = 102, // 2 x f64
395 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
640 case v2f64:
778 case v2f64:
921 case v2f64: return TypeSize::Fixed(128);
1239 if (NumElements == 2) return MVT::v2f64;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp892 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
939 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
940 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
964 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
965 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
966 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
967 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
968 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
969 setOperationAction(ISD::FROUND, MVT::v2f64, Lega
[all...]
H A DPPCTargetTransformInfo.cpp1133 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
H A DPPCISelDAGToDAG.cpp4207 else if (VecVT == MVT::v2f64)
4214 else if (VecVT == MVT::v2f64)
4221 else if (VecVT == MVT::v2f64)
5488 else if (N->getValueType(0) == MVT::v2f64 ||
5500 if (Subtarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp110 addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
405 // There should be no need to check for float types other than v2f64
408 setOperationAction(ISD::FP_TO_SINT, MVT::v2f64, Legal);
410 setOperationAction(ISD::FP_TO_UINT, MVT::v2f64, Legal);
412 setOperationAction(ISD::SINT_TO_FP, MVT::v2f64, Legal);
414 setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal);
417 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2f64, Legal);
419 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2f64, Legal);
421 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2f64, Legal);
423 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2f64, Lega
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp67 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
80 MVT::v2f64}) {
100 for (auto T : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
171 MVT::v2f64})
176 MVT::v2f64})
187 MVT::v2f64})
195 MVT::v2f64})
212 for (auto T : {MVT::v4f32, MVT::v2f64})
222 for (auto T : {MVT::v2i64, MVT::v2f64})
271 MVT::v2f64}) {
[all...]
H A DWebAssemblyFastISel.cpp143 case MVT::v2f64:
703 case MVT::v2f64:
810 case MVT::v2f64:
1361 case MVT::v2f64:
H A DWebAssemblyAsmPrinter.cpp64 MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
/netbsd-current/external/apache2/llvm/dist/clang/lib/Headers/
H A Dmsa.h32 typedef double v2f64 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/mips/
H A Dmsa.h49 typedef double v2f64 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/gpl3/gcc/dist/gcc/config/mips/
H A Dmsa.h49 typedef double v2f64 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp281 TRI->isTypeLegalForClass(*RC, MVT::v2f64))
359 TRI->isTypeLegalForClass(*RC, MVT::v2f64))
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp99 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
100 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v4i32);
175 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
181 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
219 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
220 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
261 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
262 setTruncStoreAction(MVT::v2f64, MVT::v2f16, Expand);
344 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f64, Custom);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DValueTypes.cpp376 case MVT::v2f64:
/netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenTarget.cpp166 case MVT::v2f64: return "MVT::v2f64";
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp137 case MVT::v2f64:
438 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
439 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
2291 case MVT::v2f64:
4772 case MVT::v2f64:

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