Searched refs:v16i8 (Results 1 - 25 of 35) sorted by relevance

12

/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp375 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand.
376 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand.
377 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
468 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence
469 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
472 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence
473 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
677 { ISD::SHL, MVT::v16i8, 1 },
678 { ISD::SRL, MVT::v16i8, 2 },
679 { ISD::SRA, MVT::v16i8,
1494 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, member in class:MVT
1507 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, member in class:MVT
1514 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm member in class:MVT
1521 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // widen to zmm member in class:MVT
1669 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, member in class:MVT
1680 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, member in class:MVT
1684 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, member in class:MVT
1691 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, // vpsllw+vptestmb member in class:MVT
[all...]
H A DX86ISelLowering.cpp913 addRegisterClass(MVT::v16i8, Subtarget.hasVLX() ? &X86::VR128XRegClass
934 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
939 setOperationAction(ISD::MULHU, MVT::v16i8, Custom);
940 setOperationAction(ISD::MULHS, MVT::v16i8, Custom);
945 setOperationAction(ISD::SMULO, MVT::v16i8, Custom);
946 setOperationAction(ISD::UMULO, MVT::v16i8, Custom);
952 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
955 setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
956 setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom);
959 setOperationAction(ISD::UADDSAT, MVT::v16i8, Lega
[all...]
H A DX86InterleavedAccess.cpp421 if (VT == MVT::v16i8) {
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp68 .Case("v16i8", MVT::v16i8)
137 case MVT::v16i8:
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp470 {ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 3},
471 {ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 3},
472 {ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1},
473 {ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1},
501 {ISD::TRUNCATE, MVT::v16i32, MVT::v16i8, 3},
502 {ISD::TRUNCATE, MVT::v16i16, MVT::v16i8, 1},
595 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
596 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
599 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
1159 {ISD::VECTOR_SHUFFLE, MVT::v16i8,
1603 {ISD::ADD, MVT::v16i8, 1}, member in class:MVT
[all...]
H A DARMSelectionDAGInfo.cpp311 Src = DAG.getSplatBuildVector(MVT::v16i8, dl,
H A DARMISelLowering.cpp257 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
804 addQRTypeForNEON(MVT::v16i8);
921 // v8i8/v16i8 vcnt instruction.
938 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
948 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
1594 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1822 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8))
6227 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
6231 // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds.
6663 VT = is128Bits ? MVT::v16i8
[all...]
H A DARMISelDAGToDAG.cpp1809 else if ((CanChangeType || LoadedVT == MVT::v16i8) &&
2105 case MVT::v16i8: OpcodeIndex = 0; break;
2250 case MVT::v16i8: OpcodeIndex = 0; break;
2948 case MVT::v16i8: OpcodeIndex = 0; break;
4059 case MVT::v16i8: Opc = ARM::VZIPq8; break;
4082 case MVT::v16i8: Opc = ARM::VUZPq8; break;
4104 case MVT::v16i8: Opc = ARM::VTRNq8; break;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp3567 } else if (VT == MVT::v16i8) {
3594 } else if (VT == MVT::v16i8) {
3621 } else if (VT == MVT::v16i8) {
3648 } else if (VT == MVT::v16i8) {
3675 } else if (VT == MVT::v16i8) {
3702 } else if (VT == MVT::v16i8) {
3729 } else if (VT == MVT::v16i8) {
3756 } else if (VT == MVT::v16i8) {
3783 } else if (VT == MVT::v16i8) {
3807 if (VT == MVT::v16i8 || V
[all...]
H A DAArch64TargetTransformInfo.cpp233 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
244 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
257 static const auto ValidAbsTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16,
624 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
656 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
657 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
658 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
659 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
690 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 },
691 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2
1628 {ISD::ADD, MVT::v16i8, 1}, member in class:MVT
[all...]
H A DAArch64ISelLowering.cpp257 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
272 addQRTypeForNEON(MVT::v16i8);
997 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v16i8, MVT::v16i32);
998 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v16i8, MVT::v16i32);
1027 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Legal);
1038 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1056 MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
1072 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) {
1196 MVT::v2f64, MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
1279 for (auto VT : {MVT::v16i8, MV
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h77 v16i8 = 30, // 16 x i8
391 return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 ||
528 case v16i8:
712 case v16i8:
913 case v16i8:
1151 if (NumElements == 16) return MVT::v16i8;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp62 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass);
79 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
134 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
162 for (auto T : {MVT::v16i8, MVT::v8i16})
166 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
170 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
175 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
181 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
186 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
191 setOperationAction(ISD::MUL, MVT::v16i8, Expan
[all...]
H A DWebAssemblyFastISel.cpp138 case MVT::v16i8:
683 case MVT::v16i8:
795 case MVT::v16i8:
1356 case MVT::v16i8:
H A DWebAssemblyExplicitLocals.cpp174 return MVT::v16i8;
H A DWebAssemblyAsmPrinter.cpp63 for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp715 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
764 // We promote all shuffles to v16i8.
766 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
841 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
871 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
875 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
884 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
922 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
927 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
946 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Lega
2297 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); member in class:MVT
[all...]
H A DPPCTargetTransformInfo.cpp1130 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
/netbsd-current/external/apache2/llvm/dist/clang/lib/Headers/
H A Dmsa.h14 typedef signed char v16i8 __attribute__((vector_size(16), aligned(16))); typedef
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/mips/
H A Dmsa.h31 typedef signed char v16i8 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/gpl3/gcc/dist/gcc/config/mips/
H A Dmsa.h31 typedef signed char v16i8 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp272 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
350 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DValueTypes.cpp232 case MVT::v16i8:
/netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenTarget.cpp97 case MVT::v16i8: return "MVT::v16i8";
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp105 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
1422 case MVT::v16i8:
3781 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
3782 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
3795 SDValue Tmp = DAG.getSplatBuildVector(MVT::v16i8, DL,
3801 SDValue Tmp = DAG.getSplatBuildVector(MVT::v16i8, DL,
4521 Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]);
4526 return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0],
4566 SDValue Mask = DAG.getBuildVector(MVT::v16i8, DL, IndexNodes);
4569 return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Mas
[all...]

Completed in 330 milliseconds

12