Searched refs:tx_conf_write (Results 1 - 18 of 18) sorted by relevance

/netbsd-current/sys/arch/hpcmips/tx/
H A Dtx39power.c113 tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
122 tx_conf_write(tc, TX39_POWERCTRL_REG, reg);
171 tx_conf_write(tc, TX39_INTRENABLE6_REG, TX39_INTRENABLE6_GLOBALEN);
172 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0);
173 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0);
174 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0);
175 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0);
176 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0);
178 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0);
179 tx_conf_write(t
[all...]
H A Dtx39spi.c78 tx_conf_write(tc, TX39_SPICTRL_REG, reg);
79 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIBUFAVAILINT);
80 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIERRINT);
81 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIRCVINT);
82 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIEMPTYINT);
148 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIBUFAVAILINT);
150 tx_conf_write(tc, TX39_SPITXHOLD_REG , w & 0xffff);
160 tx_conf_write(tc, TX39_INTRCLEAR5_REG, TX39_INTRSTATUS5_SPIRCVINT);
174 tx_conf_write(tc, TX39_SPICTRL_REG, reg);
182 tx_conf_write(t
[all...]
H A Dtx39icu.c253 tx_conf_write(tc, TX39_INTRENABLE1_REG, 0);
254 tx_conf_write(tc, TX39_INTRENABLE2_REG, 0);
255 tx_conf_write(tc, TX39_INTRENABLE3_REG, 0);
256 tx_conf_write(tc, TX39_INTRENABLE4_REG, 0);
257 tx_conf_write(tc, TX39_INTRENABLE5_REG, 0);
259 tx_conf_write(tc, TX39_INTRENABLE7_REG, 0);
260 tx_conf_write(tc, TX39_INTRENABLE8_REG, 0);
266 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
270 tx_conf_write(tc, TX39_INTRCLEAR1_REG,
272 tx_conf_write(t
[all...]
H A Dtx39clock.c120 tx_conf_write(tc, TX39_TIMERCONTROL_REG, 0);
125 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
189 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
228 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
232 tx_conf_write(tc, TX39_TIMERCONTROL_REG, reg);
264 tx_conf_write(tc, TX39_TIMERPERIODIC_REG, reg);
271 tx_conf_write(tc, TX39_INTRENABLE6_REG, reg);
308 tx_conf_write(tc, TX39_TIMERALARMHI_REG, t.t_hi);
309 tx_conf_write(tc, TX39_TIMERALARMLO_REG, t.t_lo);
H A Dtx3912video.c159 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
222 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
230 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, val);
323 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
408 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
417 tx_conf_write(tc, TX3912_VIDEOCTRL3_REG, reg);
428 tx_conf_write(tc, TX3912_VIDEOCTRL4_REG, reg);
467 tx_conf_write(tc, TX3912_VIDEOCTRL2_REG, reg);
480 tx_conf_write(tc, TX3912_VIDEOCTRL1_REG, reg);
487 tx_conf_write(t
[all...]
H A Dtx39sib.c204 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
212 tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);
219 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
231 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
246 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
255 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
259 tx_conf_write(tc, TX39_SIBCTRL_REG, reg);
314 tx_conf_write(tc, TX39_INTRSTATUS1_REG, TX39_INTRSTATUS1_SIBSF0INT);
341 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
359 tx_conf_write(t
[all...]
H A Dtxcom.c320 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
323 tx_conf_write(tc, ofs, 0);
350 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
357 tx_conf_write(tc, ofs, reg);
363 tx_conf_write(tc, ofs, reg);
395 tx_conf_write(tc, TX39_UARTCTRL1_REG(slot), reg);
400 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
435 tx_conf_write(tc, ofs, reg);
478 tx_conf_write(tc, TX39_UARTTXHOLD_REG(chip->sc_slot),
500 tx_conf_write(chi
[all...]
H A Dtxcsbus.c280 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg);
290 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg);
299 tx_conf_write(tc, TX39_MEMCONFIG0_REG, reg);
307 tx_conf_write(tc, TX39_MEMCONFIG1_REG, reg);
326 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg);
347 tx_conf_write(tc, TX39_MEMCONFIG3_REG, reg);
H A Dtx39ir.c99 tx_conf_write(tc, TX39_IRCTRL1_REG, reg);
104 tx_conf_write(tc, TX39_CLOCKCTRL_REG, reg);
H A Dtx39var.h97 #define tx_conf_write(t, reg, val) ( \ macro
H A Dtx39biu.c104 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
156 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
159 tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
H A Dtx39io.c235 tx_conf_write(tc, TX39_IOMFIODATAOUT_REG, reg);
320 tx_conf_write(tc, TX39_IOCTRL_REG, reg);
400 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
/netbsd-current/sys/arch/hpcmips/dev/
H A Ducbsnd.c274 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
285 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
289 tx_conf_write(tc, TX39_SIBCTRL_REG,
299 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
322 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
362 tx_conf_write(tc, TX39_SIBSNDTXSTART_REG,
366 tx_conf_write(tc, TX39_SIBSIZE_REG,
369 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, TX39_SIBSF0_SNDVALID);
374 tx_conf_write(tc, TX39_SIBDMACTRL_REG, reg);
402 tx_conf_write(t
[all...]
H A Dteliosio.c265 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
272 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
290 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
299 tx_conf_write(tc, TX392X_IODATAINOUT_REG, reg);
H A Doptpoint.c165 tx_conf_write(tc, TX39_INTRCLEAR4_REG,
190 tx_conf_write(tc, TX39_INTRCLEAR4_REG, TX39_INTRSTATUS4_OPTPOINTINT);
284 tx_conf_write(tc, TX39_INTRCLEAR4_REG, TX39_INTRSTATUS4_OPTPOINTINT);
H A Ducbtp.c573 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
623 tx_conf_write(tc, TX39_SIBSF0CTRL_REG, reg);
H A Dit8368.c568 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32);
/netbsd-current/sys/arch/hpcmips/stand/pbsdboot/
H A Dtx39xx.c57 tx_conf_write(tx_chipset_tag_t t, int reg, u_int32_t val) function

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