/netbsd-current/sys/arch/hpcmips/tx/ |
H A D | tx39icu.c | 234 regs[0] = tx_conf_read(tc, TX39_INTRSTATUS6_REG); 235 regs[1] = tx_conf_read(tc, TX39_INTRSTATUS1_REG); 236 regs[2] = tx_conf_read(tc, TX39_INTRSTATUS2_REG); 237 regs[3] = tx_conf_read(tc, TX39_INTRSTATUS3_REG); 238 regs[4] = tx_conf_read(tc, TX39_INTRSTATUS4_REG); 239 regs[5] = tx_conf_read(tc, TX39_INTRSTATUS5_REG); 241 regs[7] = tx_conf_read(tc, TX39_INTRSTATUS7_REG); 242 regs[8] = tx_conf_read(tc, TX39_INTRSTATUS8_REG); 264 reg = tx_conf_read(tc, TX39_INTRENABLE6_REG); 271 tx_conf_read(t [all...] |
H A D | tx39power.c | 111 reg = tx_conf_read(tc, TX39_POWERCTRL_REG); 116 reg = tx_conf_read(tc, TX39_POWERCTRL_REG); 157 reg = tx_conf_read(tc, TX39_POWERCTRL_REG); 160 iregs[0] = tx_conf_read(tc, TX39_INTRENABLE6_REG); 161 iregs[1] = tx_conf_read(tc, TX39_INTRENABLE1_REG); 162 iregs[2] = tx_conf_read(tc, TX39_INTRENABLE2_REG); 163 iregs[3] = tx_conf_read(tc, TX39_INTRENABLE3_REG); 164 iregs[4] = tx_conf_read(tc, TX39_INTRENABLE4_REG); 165 iregs[5] = tx_conf_read(tc, TX39_INTRENABLE5_REG); 167 iregs[7] = tx_conf_read(t [all...] |
H A D | tx39spi.c | 76 reg = tx_conf_read(tc, TX39_SPICTRL_REG); 138 return tx_conf_read(sc->sc_tc, TX39_SPICTRL_REG) & (TX39_SPICTRL_EMPTY); 146 while(!(tx_conf_read(tc, TX39_INTRSTATUS5_REG) & TX39_INTRSTATUS5_SPIBUFAVAILINT)) 158 while(!(tx_conf_read(tc, TX39_INTRSTATUS5_REG) & TX39_INTRSTATUS5_SPIRCVINT)) 162 return tx_conf_read(tc, TX39_SPIRXHOLD_REG) & 0xffff; 169 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG); 181 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG); 189 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG); 197 txreg_t reg = tx_conf_read(tc, TX39_SPICTRL_REG); 209 txreg_t reg = tx_conf_read(t [all...] |
H A D | tx39clock.c | 123 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 180 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 204 oreglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 205 reglo = tx_conf_read(tc, TX39_TIMERRTCLO_REG); 207 oreghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 208 reghi = tx_conf_read(tc, TX39_TIMERRTCHI_REG); 224 reg = tx_conf_read(tc, TX39_TIMERCONTROL_REG); 246 return tx_conf_read(tc, TX39_TIMERRTCLO_REG); 261 reg = tx_conf_read(tc, TX39_TIMERPERIODIC_REG); 269 reg = tx_conf_read(t [all...] |
H A D | tx39io.c | 230 reg = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG); 244 return (tx_conf_read(sc->sc_tc, TX39_IOMFIODATAIN_REG) & (1 << port)); 272 stat_mfio->dir = tx_conf_read(tc, TX39_IOMFIODATADIR_REG); 273 stat_mfio->in = tx_conf_read(tc, TX39_IOMFIODATAIN_REG); 274 stat_mfio->out = tx_conf_read(tc, TX39_IOMFIODATAOUT_REG); 275 stat_mfio->power = tx_conf_read(tc, TX39_IOMFIOPOWERDWN_REG); 276 stat_mfio->u.select = tx_conf_read(tc, TX39_IOMFIODATASEL_REG); 287 txreg_t reg = tx_conf_read(sc->sc_tc, TX39_IOCTRL_REG); 312 reg = tx_conf_read(tc, TX39_IOCTRL_REG); 333 reg = tx_conf_read(t [all...] |
H A D | tx39biu.c | 101 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 106 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 154 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 157 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG); 179 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 229 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 257 reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
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H A D | tx39sib.c | 207 reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG); 217 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); 229 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); 244 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); 251 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); 315 for (i = 0; (!(tx_conf_read(tc, TX39_INTRSTATUS1_REG) & 362 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG); 384 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); 405 reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG);
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H A D | tx39ir.c | 97 reg = tx_conf_read(tc, TX39_IRCTRL1_REG); 102 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); 130 reg = tx_conf_read(tc, TX39_IRCTRL1_REG);
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H A D | txcsbus.c | 278 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 286 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 297 reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG); 303 reg = tx_conf_read(tc, TX39_MEMCONFIG1_REG); 311 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG); 332 reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);
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H A D | tx39var.h | 95 #define tx_conf_read(t, reg) ( \ macro
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H A D | txcom.c | 318 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); 348 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); 355 reg = tx_conf_read(tc, ofs); 360 reg = tx_conf_read(tc, ofs); 367 while(!(tx_conf_read(tc, ofs) & TX39_UARTCTRL1_UARTON) && 389 reg = tx_conf_read(tc, TX39_UARTCTRL1_REG(slot)); 398 reg = tx_conf_read(tc, TX39_CLOCKCTRL_REG); 411 if (tx_conf_read(tc, ofs) & TX39_UARTCTRL1_EMPTY) 429 reg = tx_conf_read(tc, ofs); 452 while(!(TX39_UARTCTRL1_RXHOLDFULL & tx_conf_read(t [all...] |
H A D | tx3912video.c | 157 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 220 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 228 val = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 308 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 319 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 406 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 445 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG); 476 reg = tx_conf_read(tc, TX3912_VIDEOCTRL1_REG);
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H A D | tx39.c | 134 rev = tx_conf_read(tc, TX3922_REVISION_REG);
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/netbsd-current/sys/arch/hpcmips/dev/ |
H A D | teliosio.c | 230 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); 259 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); 270 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); 288 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG); 295 reg = tx_conf_read(tc, TX392X_IODATAINOUT_REG);
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H A D | ucbsnd.c | 288 reg = tx_conf_read(tc, TX39_SIBCTRL_REG); 305 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG); 372 reg = tx_conf_read(tc, TX39_SIBDMACTRL_REG); 443 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG); 467 reg = tx_conf_read(tc, TX39_SIBCTRL_REG);
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H A D | it8368.c | 553 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 575 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
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H A D | ucbtp.c | 578 reg = tx_conf_read(tc, TX39_SIBSF0STAT_REG);
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/netbsd-current/sys/arch/hpcmips/stand/pbsdboot/ |
H A D | tx39xx.c | 51 tx_conf_read(tx_chipset_tag_t t, int reg) function
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