/netbsd-current/sys/dev/fdt/ |
H A D | display_timing.c | 45 display_timing_parse(int phandle, struct display_timing *timing) argument 47 if (GETPROP("clock-frequency", &timing->clock_freq) || 48 GETPROP("hactive", &timing->hactive) || 49 GETPROP("vactive", &timing->vactive) || 50 GETPROP("hfront-porch", &timing->hfront_porch) || 51 GETPROP("hback-porch", &timing->hback_porch) || 52 GETPROP("hsync-len", &timing->hsync_len) || 53 GETPROP("vfront-porch", &timing->vfront_porch) || 54 GETPROP("vback-porch", &timing->vback_porch) || 55 GETPROP("vsync-len", &timing [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/bios/ |
H A D | nouveau_nvkm_subdev_bios_timing.c | 31 #include <subdev/bios/timing.h> 38 u32 timing = 0; local 42 timing = nvbios_rd32(bios, bit_P.offset + 4); 45 timing = nvbios_rd32(bios, bit_P.offset + 8); 47 if (timing) { 48 *ver = nvbios_rd08(bios, timing + 0); 51 *hdr = nvbios_rd08(bios, timing + 1); 52 *cnt = nvbios_rd08(bios, timing + 2); 53 *len = nvbios_rd08(bios, timing + 3); 56 return timing; 78 u32 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); local [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
H A D | dc_dsc.h | 69 const struct dc_crtc_timing *timing, 77 const struct dc_crtc_timing *timing, 80 void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
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/netbsd-current/sys/arch/arm/fdt/ |
H A D | plfb_fdt.c | 255 plfb_get_panel_timing(struct plfb_softc *sc, struct display_timing *timing) argument 262 panel_timing = of_find_firstchild_byname(panel, "panel-timing"); 266 return display_timing_parse(panel_timing, timing); 273 struct display_timing timing; local 275 if (plfb_get_panel_timing(sc, &timing) != 0) { 277 timing.hactive = 800; 278 timing.hback_porch = 128; 279 timing.hfront_porch = 24; 280 timing.hsync_len = 72; 281 timing [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dsc/ |
H A D | amdgpu_dc_dsc.c | 41 const struct dc_crtc_timing *timing) 46 if (timing->flags.DSC) { 47 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); 52 switch (timing->display_color_depth) { 77 kbps = timing->pix_clk_100hz / 10; 80 if (timing->flags.Y_ONLY != 1) { 83 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 85 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 332 /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing' 40 dc_dsc_bandwidth_in_kbps_from_timing( const struct dc_crtc_timing *timing) argument 335 get_dsc_bandwidth_range( const uint32_t min_bpp, const uint32_t max_bpp, const struct dsc_enc_caps *dsc_caps, const struct dc_crtc_timing *timing, struct dc_dsc_bw_range *range) argument 372 decide_dsc_target_bpp_x16( const struct dc_dsc_policy *policy, const struct dsc_enc_caps *dsc_common_caps, const int target_bandwidth_kbps, const struct dc_crtc_timing *timing, int *target_bpp_x16) argument 560 setup_dsc_config( const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dsc_enc_caps *dsc_enc_caps, int target_bandwidth_kbps, const struct dc_crtc_timing *timing, int min_slice_height_override, struct dc_dsc_config *dsc_cfg) argument 882 dc_dsc_compute_bandwidth_range( const struct display_stream_compressor *dsc, const uint32_t dsc_min_slice_height_override, const uint32_t min_bpp, const uint32_t max_bpp, const struct dsc_dec_dpcd_caps *dsc_sink_caps, const struct dc_crtc_timing *timing, struct dc_dsc_bw_range *range) argument 911 dc_dsc_compute_config( const struct display_stream_compressor *dsc, const struct dsc_dec_dpcd_caps *dsc_sink_caps, const uint32_t dsc_min_slice_height_override, uint32_t target_bandwidth_kbps, const struct dc_crtc_timing *timing, struct dc_dsc_config *dsc_cfg) argument 930 dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, struct dc_dsc_policy *policy) argument [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
H A D | amdgpu_dce110_timing_generator_v.c | 249 const struct dc_crtc_timing *timing) 251 uint32_t vsync_offset = timing->v_border_bottom + 252 timing->v_front_porch; 253 uint32_t v_sync_start = timing->v_addressable + vsync_offset; 255 uint32_t hsync_offset = timing->h_border_right + 256 timing->h_front_porch; 257 uint32_t h_sync_start = timing->h_addressable + hsync_offset; 268 timing->h_total - 1, 277 timing->v_total - 1, 285 tmp = timing 247 dce110_timing_generator_v_program_blanking( struct timing_generator *tg, const struct dc_crtc_timing *timing) argument 389 dce110_timing_generator_v_enable_advanced_request( struct timing_generator *tg, bool enable, const struct dc_crtc_timing *timing) argument 441 dce110_timing_generator_v_program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, int vready_offset, int vstartup_start, int vupdate_offset, int vupdate_width, const enum signal_type signal, bool use_vbios) argument [all...] |
H A D | dce110_timing_generator.h | 128 /* determine if given timing can be supported by TG */ 131 const struct dc_crtc_timing *timing, 136 /* Program timing generator with given timing */ 202 /* Fully program CRTC timing in timing generator */ 205 const struct dc_crtc_timing *timing); 249 const struct dc_crtc_timing *timing); 261 const struct dc_crtc_timing *timing, 275 const struct dc_crtc_timing *timing); [all...] |
H A D | amdgpu_dce110_timing_generator.c | 60 * So we can create dce110 timing generator to use it. 72 struct dc_crtc_timing *timing) 74 if (timing->flags.INTERLACE == 1) { 75 if (timing->v_front_porch < 2) 76 timing->v_front_porch = 2; 78 if (timing->v_front_porch < 1) 79 timing->v_front_porch = 1; 262 const struct dc_crtc_timing *timing) 273 if (timing->flags.HORZ_COUNT_BY_TWO) 306 * to programming the timing 70 dce110_timing_generator_apply_front_porch_workaround( struct timing_generator *tg, struct dc_crtc_timing *timing) argument 260 program_horz_count_by_2( struct timing_generator *tg, const struct dc_crtc_timing *timing) argument 606 dce110_timing_generator_program_blanking( struct timing_generator *tg, const struct dc_crtc_timing *timing) argument 1119 dce110_timing_generator_validate_timing( struct timing_generator *tg, const struct dc_crtc_timing *timing, enum signal_type signal) argument 1419 dce110_timing_generator_enable_advanced_request( struct timing_generator *tg, bool enable, const struct dc_crtc_timing *timing) argument 1963 dce110_tg_program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, int vready_offset, int vstartup_start, int vupdate_offset, int vupdate_width, const enum signal_type signal, bool use_vbios) argument 2023 dce110_tg_validate_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing) argument [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
H A D | nouveau_nvkm_subdev_fb_ramnv50.c | 39 #include <subdev/bios/timing.h> 78 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) argument 103 timing[6] = (0x2d + T(CL) - T(CWL) + 109 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | 114 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); 115 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | 119 timing[2] = (T(CWL) - 1) << 24 | 123 timing[3] = (unkt3b - 2 + T(CL)) << 24 | 127 timing[4] = (cur4 & 0xffff0000) | 130 timing[ 156 nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing) argument 238 u32 timing[9]; local [all...] |
H A D | nouveau_nvkm_subdev_fb_sddr3.c | 85 /* XXX: NV50: Get CWL from the timing register */ 94 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; 95 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; 96 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
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H A D | nouveau_nvkm_subdev_fb_sddr2.c | 79 CL = (ram->next->bios.timing[1] & 0x0000001f); 80 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
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H A D | nouveau_nvkm_subdev_fb_gddr3.c | 90 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; 91 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; 92 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
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H A D | nouveau_nvkm_subdev_fb_ramgt215.c | 39 #include <subdev/bios/timing.h> 353 gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing) argument 379 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); 380 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | 384 timing[2] = (T(CWL) - 1) << 24 | 388 timing[3] = (cur3 & 0x00ff0000) | 392 timing[4] = T(20) << 24 | 396 timing[5] = T(RFC) << 24 | 400 timing[6] = (0x5a + T(CL)) << 16 | 403 timing[ 513 u32 timing[9]; local [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
H A D | amdgpu_dce110_clk_mgr.c | 106 uint32_t vertical_total_min = stream->timing.v_total; 111 vertical_blank_in_pixels = stream->timing.h_total * 113 - stream->timing.v_addressable); 115 * 10000 / stream->timing.pix_clk_100hz; 168 cfg->v_refresh = stream->timing.pix_clk_100hz * 100; 169 cfg->v_refresh /= stream->timing.h_total; 170 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) 171 / stream->timing.v_total; 241 const struct dc_crtc_timing *timing = local 242 &context->streams[0]->timing; [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
H A D | amdgpu_dce120_timing_generator.c | 105 /* determine if given timing can be supported by TG */ 108 const struct dc_crtc_timing *timing, 111 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; 113 (timing->v_total - timing->v_addressable - 114 timing->v_border_top - timing->v_border_bottom) * 120 timing, 126 timing->h_sync_width < tg110->min_h_sync_width || 127 timing 106 dce120_timing_generator_validate_timing( struct timing_generator *tg, const struct dc_crtc_timing *timing, enum signal_type signal) argument 133 dce120_tg_validate_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing) argument 433 dce120_timing_generator_program_blanking( struct timing_generator *tg, const struct dc_crtc_timing *timing) argument 669 dce120_timing_generator_enable_advanced_request( struct timing_generator *tg, bool enable, const struct dc_crtc_timing *timing) argument 742 dce120_tg_program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, int vready_offset, int vstartup_start, int vupdate_offset, int vupdate_width, const enum signal_type signal, bool use_vbios) argument [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/modules/info_packet/ |
H A D | amdgpu_info_packet.c | 152 if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) { 232 switch (stream->timing.timing_3d_format) { 332 switch (stream->timing.pixel_encoding) { 351 switch (stream->timing.pixel_encoding) { 387 switch (stream->timing.display_color_depth) { 416 info_packet->sb[17] |= 0x80; /* DB17 bit 7 set to 1 for CEA timing. */ 454 format = stream->timing.timing_3d_format; 458 if (stream->timing.hdmi_vic != 0 459 && stream->timing.h_total >= 3840 460 && stream->timing [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
H A D | amdgpu_dce80_timing_generator.c | 114 const struct dc_crtc_timing *timing, 123 program_pix_dur(tg, timing->pix_clk_100hz); 125 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); 131 const struct dc_crtc_timing *timing) 151 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { 113 program_timing(struct timing_generator *tg, const struct dc_crtc_timing *timing, int vready_offset, int vstartup_start, int vupdate_offset, int vupdate_width, const enum signal_type signal, bool use_vbios) argument 128 dce80_timing_generator_enable_advanced_request( struct timing_generator *tg, bool enable, const struct dc_crtc_timing *timing) argument
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
H A D | amdgpu_dcn10_opp.c | 315 const struct dc_crtc_timing *timing) 319 uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; 320 uint32_t space1_size = timing->v_total - timing->v_addressable; 322 uint32_t space2_size = timing->v_total - timing->v_addressable; 340 if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE) 312 opp1_program_stereo( struct output_pixel_processor *opp, bool enable, const struct dc_crtc_timing *timing) argument
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H A D | amdgpu_dcn10_optc.c | 54 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) argument 56 if (timing->flags.INTERLACE == 1) { 57 if (timing->v_front_porch < 2) 58 timing->v_front_porch = 2; 60 if (timing->v_front_porch < 1) 61 timing->v_front_porch = 1; 140 * program_timing_generator used by mode timing set 174 /* Load horizontal timing */ 516 const struct dc_crtc_timing *timing) 523 ASSERT(timing ! 514 optc1_validate_timing( struct timing_generator *optc, const struct dc_crtc_timing *timing) argument 1190 optc1_enable_stereo(struct timing_generator *optc, const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) argument 1222 optc1_program_stereo(struct timing_generator *optc, const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) argument 1527 optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) argument [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
H A D | amdgpu_dc_link_hwss.c | 122 pipes[i].stream->timing.pix_clk_100hz; 433 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 434 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 435 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 436 dsc_cfg.color_depth = stream->timing.display_color_depth; 437 dsc_cfg.dc_dsc_cfg = stream->timing [all...] |
H A D | amdgpu_dc_stream.c | 56 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && 112 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; 114 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); 115 stream->timing.dsc_cfg.num_slices_h = 0; 116 stream->timing.dsc_cfg.num_slices_v = 0; 117 stream->timing.dsc_cfg.bits_per_pixel = 128; 118 stream->timing.dsc_cfg.block_pred_enable = 1; 119 stream->timing.dsc_cfg.linebuf_depth = 9; 120 stream->timing [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/modules/freesync/ |
H A D | amdgpu_freesync.c | 120 * 10000) * stream->timing.h_total, 121 stream->timing.pix_clk_100hz)); 138 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), 139 stream->timing.h_total), 1000000); 142 if (v_total < stream->timing.v_total) { 143 ASSERT(v_total < stream->timing.v_total); 144 v_total = stream->timing.v_total; 164 duration_in_us) * (stream->timing.pix_clk_100hz / 10)), 165 stream->timing.h_total), 1000); 168 if (v_total < stream->timing [all...] |
/netbsd-current/external/gpl3/gdb.old/dist/sim/lm32/ |
H A D | lm32.c | 97 return idesc->timing->units[unit_num].done;
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/netbsd-current/external/gpl3/gdb/dist/sim/lm32/ |
H A D | lm32.c | 98 return idesc->timing->units[unit_num].done;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
H A D | amdgpu_dcn20_optc.c | 83 * Options: anytime, start of frame, dp start of frame (range timing) 128 /* You can control the GSL timing by limiting GSL to a window (X,Y) */ 215 bool optc2_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) argument 217 return optc1_is_two_pixels_per_containter(timing); 241 struct dc_crtc_timing *timing) 244 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) 270 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 272 else if (timing 240 optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, struct dc_crtc_timing *timing) argument [all...] |