/netbsd-current/external/gpl3/gdb.old/dist/ld/testsuite/ld-mn10300/ |
H A D | i126256-1.c | 2 sub0 (int i) function
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/netbsd-current/external/gpl3/gdb.old/dist/ld/testsuite/ld-tic6x/ |
H A D | shlib-1.s | 10 .global sub0 11 .type sub0, @function 12 sub0: label 18 call .s2 (sub0) 27 .size sub0, .-sub0 35 .long sub0
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H A D | shlib-app-1r.s | 5 callp .s2 sub0, B3 6 b .s2 sub0
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H A D | shlib-app-1.s | 6 callp .s2 sub0, B3 7 b .s2 sub0
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/netbsd-current/external/gpl3/binutils/dist/include/vms/ |
H A D | dcx.h | 35 unsigned char sub0[2]; member in struct:vms_dcxmap
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/netbsd-current/external/gpl3/gdb.old/dist/include/vms/ |
H A D | dcx.h | 35 unsigned char sub0[2]; member in struct:vms_dcxmap
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/netbsd-current/external/gpl3/gdb/dist/include/vms/ |
H A D | dcx.h | 35 unsigned char sub0[2]; member in struct:vms_dcxmap
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/netbsd-current/external/gpl3/binutils.old/dist/include/vms/ |
H A D | dcx.h | 35 unsigned char sub0[2]; member in struct:vms_dcxmap
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 202 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass)); 209 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); 216 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); 224 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); 231 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); 238 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); 245 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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H A D | R600RegisterInfo.cpp | 26 R600::sub0, R600::sub1, R600::sub2, R600::sub3,
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H A D | AMDGPUInstructionSelector.cpp | 259 case AMDGPU::sub0: 353 MachineOperand Lo1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub0)); 354 MachineOperand Lo2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub0)); 389 .addImm(AMDGPU::sub0) 1648 unsigned SubReg = Is64 ? AMDGPU::sub0_sub1 : AMDGPU::sub0; 1814 return AMDGPU::sub0; 1825 return AMDGPU::sub0; 1876 .addReg(SrcReg, 0, AMDGPU::sub0); 2007 .addImm(AMDGPU::sub0) 2063 unsigned SubReg = InReg ? AMDGPU::sub0 [all...] |
H A D | SIInstrInfo.cpp | 1697 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); 1742 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) 1908 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); 1974 for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) { 2011 .addImm(AMDGPU::sub0) 2197 .addReg(PCReg, RegState::Define, AMDGPU::sub0) 2198 .addReg(PCReg, 0, AMDGPU::sub0) 2207 .addReg(PCReg, RegState::Define, AMDGPU::sub0) 2208 .addReg(PCReg, 0, AMDGPU::sub0) 2576 AMDGPU::sub0, AMDGP [all...] |
H A D | SIFrameLowering.cpp | 166 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); 229 FlatScrInitLo = TRI->getSubReg(FlatScrInit, AMDGPU::sub0); 267 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); 604 Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); 642 Register ScratchRsrcSub0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
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H A D | R600MachineScheduler.cpp | 255 case R600::sub0:
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H A D | AMDGPUISelDAGToDAG.cpp | 641 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), 788 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); 1022 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); 1712 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); 1998 CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32), 2409 unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1; 2786 (VecSize > 32) ? AMDGPU::sub0_sub1 : AMDGPU::sub0, SDLoc(In), 2792 (VecSize > 32) ? AMDGPU::sub0_sub1 : AMDGPU::sub0, SDLoc(In), 2816 Lo, CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32),
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H A D | SIRegisterInfo.cpp | 277 assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 && 281 getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() && 440 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass); 1773 ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0); 2185 // %2 = REG_SEQUENCE %0, sub0, %1, sub1, %2, sub2 2186 // %3 = COPY %2, sub0
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H A D | SIISelLowering.cpp | 3643 return std::make_pair(AMDGPU::sub0, Offset); 3863 .addImm(AMDGPU::sub0); 3870 .addImm(AMDGPU::sub0); 3921 MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass); 3926 MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass); 3938 .addImm(AMDGPU::sub0) 3973 TRI->getSubRegClass(Src0RC, AMDGPU::sub0); 3978 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); 3980 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); 4005 .addImm(AMDGPU::sub0) [all...] |
H A D | SILoadStoreOptimizer.cpp | 1064 unsigned SubRegIdx0 = (CI.EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1; 1554 {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3}, 1723 .addImm(AMDGPU::sub0) 1767 // REG_SEQUENCE %LO:vgpr_32, %subreg.sub0, %HI:vgpr_32, %subreg.sub1
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H A D | AMDGPURegisterBankInfo.cpp | 925 .addReg(UnmergePiece, 0, AMDGPU::sub0); 1836 .addUse(SrcReg, 0, AMDGPU::sub0); 1843 .addImm(AMDGPU::sub0)
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/netbsd-current/external/lgpl3/gmp/dist/mpn/ia64/ |
H A D | add_n_sub_n.asm | 128 cmpltu p10, p0 = u0, v0 C borrow from sub0 M I 186 cmpltu p12, p0 = u2, v2 C borrow from sub0 M I 246 cmpltu p10, p0 = u0, v0 C borrow from sub0 M I
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.cpp | 276 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 770 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 773 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 786 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 790 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
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/netbsd-current/external/gpl3/gcc.old/dist/libphobos/src/std/ |
H A D | string.d | 724 dchar sub0 = subr.front; // cache first character of sub[] 729 return indexOf(s, sub0, cs); 732 sub0 = toLower(sub0); 742 if (c2 == sub0)
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/netbsd-current/external/gpl3/gcc/dist/libphobos/src/std/ |
H A D | string.d | 856 dchar sub0 = subr.front; // cache first character of sub[] 861 return indexOf(s, sub0, cs); 864 sub0 = toLower(sub0); 874 if (c2 == sub0)
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUBaseInfo.cpp | 1468 const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
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/netbsd-current/external/gpl3/binutils/dist/bfd/ |
H A D | vms-lib.c | 620 sbm_off = bfd_getl16 (map->sub0);
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