Searched refs:sdma_cntl (Results 1 - 6 of 6) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_sdma_v2_4.c | 1015 u32 sdma_cntl; local
1021 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1022 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1023 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1026 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1027 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1028 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1037 sdma_cntl
[all...] |
| H A D | amdgpu_si_dma.c | 596 u32 sdma_cntl; local
602 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);
603 sdma_cntl &= ~TRAP_ENABLE;
604 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
607 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);
608 sdma_cntl |= TRAP_ENABLE;
609 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
618 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET);
619 sdma_cntl &= ~TRAP_ENABLE;
620 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);
[all...] |
| H A D | amdgpu_cik_sdma.c | 1121 u32 sdma_cntl; local
1127 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1128 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1129 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1132 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1133 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1134 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1143 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1144 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1145 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
[all...] |
| H A D | amdgpu_sdma_v3_0.c | 1349 u32 sdma_cntl; local
1355 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1356 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1357 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1360 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1361 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1362 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1371 sdma_cntl
[all...] |
| H A D | amdgpu_sdma_v5_0.c | 1397 u32 sdma_cntl; local
1403 sdma_cntl = RREG32(reg_offset);
1404 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1406 WREG32(reg_offset, sdma_cntl);
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| H A D | amdgpu_sdma_v4_0.c | 2010 u32 sdma_cntl; local
2012 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2013 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2015 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
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