/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_arct_reg_init.c | 39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); 40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); 41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); 42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); 43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); 44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); 45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); 46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); 47 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); 48 adev->reg_offset[OSSSYS_HWI [all...] |
H A D | amdgpu_navi10_reg_init.c | 39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); 40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i])); 41 adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i])); 42 adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i])); 43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIO_BASE.instance[i])); 44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i])); 45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i])); 46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(VCN_BASE.instance[i])); 47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i])); 48 adev->reg_offset[DCE_HWI [all...] |
H A D | amdgpu_navi12_reg_init.c | 39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); 40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i])); 41 adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i])); 42 adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i])); 43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIF0_BASE.instance[i])); 44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i])); 45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i])); 46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i])); 47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i])); 48 adev->reg_offset[DCE_HWI [all...] |
H A D | amdgpu_navi14_reg_init.c | 39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); 40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i])); 41 adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i])); 42 adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i])); 43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIF0_BASE.instance[i])); 44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i])); 45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i])); 46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i])); 47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i])); 48 adev->reg_offset[DCE_HWI [all...] |
H A D | amdgpu_vega10_reg_init.c | 39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); 40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); 41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); 42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); 43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); 44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); 45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); 46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); 47 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); 48 adev->reg_offset[VCN_HWI [all...] |
H A D | mmsch_v1_0.h | 65 uint32_t reg_offset : 28; member in struct:mmsch_v1_0_cmd_direct_reg_header 70 uint32_t reg_offset : 20; member in struct:mmsch_v1_0_cmd_indirect_reg_header 103 uint32_t reg_offset, 106 direct_wt->cmd_header.reg_offset = reg_offset; 113 uint32_t reg_offset, 116 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; 125 uint32_t reg_offset, 128 direct_poll->cmd_header.reg_offset 101 mmsch_v1_0_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write *direct_wt, uint32_t *init_table, uint32_t reg_offset, uint32_t value) argument 111 mmsch_v1_0_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt, uint32_t *init_table, uint32_t reg_offset, uint32_t mask, uint32_t data) argument 123 mmsch_v1_0_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll, uint32_t *init_table, uint32_t reg_offset, uint32_t mask, uint32_t wait) argument [all...] |
H A D | soc15_common.h | 30 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 33 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 34 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ 38 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 41 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset) 44 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) 47 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) 50 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value) 55 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 64 tmp_ = RREG32(adev->reg_offset[i [all...] |
H A D | amdgpu_vega20_reg_init.c | 39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); 40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); 41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); 42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); 43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); 44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); 45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); 46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); 47 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); 48 adev->reg_offset[DF_HWI [all...] |
H A D | amdgpu_jpeg_v1_0.c | 41 static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) argument 45 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || 46 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { 48 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); 50 ring->ring[(*ptr)++] = reg_offset; 60 uint32_t reg, reg_offset, val, mask, i; local 64 reg_offset = (reg << 2); 66 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, va 350 uint32_t reg_offset = (reg << 2); local 394 uint32_t reg_offset = (reg << 2); local [all...] |
H A D | soc15.h | 51 uint32_t reg_offset; member in struct:soc15_reg_entry 61 uint32_t reg_offset; member in struct:soc15_allowed_register_entry 70 uint32_t reg_offset; member in struct:soc15_ras_field_entry 79 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
H A D | common_baco.h | 40 uint32_t reg_offset; member in struct:baco_cmd_entry 52 uint32_t reg_offset; member in struct:soc15_baco_cmd_entry
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/netbsd-current/external/gpl3/gdb.old/dist/gdb/ |
H A D | tic6x-linux-tdep.c | 96 unsigned int reg_offset; local 101 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); 102 gdb_assert (reg_offset != 0); 104 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); 109 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); 110 gdb_assert (reg_offset != 0); 112 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); 118 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); 119 gdb_assert (reg_offset != 0); 121 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); [all...] |
H A D | hppa-nbsd-tdep.c | 122 int *reg_offset; local 126 reg_offset = hppanbsd_mc_reg_offset; 137 if (reg_offset[i] != -1) 138 trad_frame_set_reg_addr (this_cache, i, base + reg_offset[i]);
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H A D | bfin-linux-tdep.c | 105 const int *reg_offset = bfin_linux_sigcontext_reg_offset; local 109 if (reg_offset[i] != -1) 110 trad_frame_set_reg_addr (this_cache, i, sigcontext + reg_offset[i]);
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H A D | amd64-nat.c | 54 int *reg_offset = amd64_native_gregset64_reg_offset; local 61 reg_offset = amd64_native_gregset32_reg_offset; 71 return reg_offset[regnum];
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/netbsd-current/external/gpl3/gdb/dist/gdb/ |
H A D | tic6x-linux-tdep.c | 97 unsigned int reg_offset; local 102 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); 103 gdb_assert (reg_offset != 0); 105 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); 110 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); 111 gdb_assert (reg_offset != 0); 113 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); 119 reg_offset = tic6x_register_sigcontext_offset (i, gdbarch); 120 gdb_assert (reg_offset != 0); 122 trad_frame_set_reg_addr (this_cache, i, base + reg_offset); [all...] |
H A D | hppa-netbsd-tdep.c | 121 int *reg_offset; local 125 reg_offset = hppanbsd_mc_reg_offset; 136 if (reg_offset[i] != -1) 137 trad_frame_set_reg_addr (this_cache, i, base + reg_offset[i]);
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H A D | bfin-linux-tdep.c | 105 const int *reg_offset = bfin_linux_sigcontext_reg_offset; local 109 if (reg_offset[i] != -1) 110 trad_frame_set_reg_addr (this_cache, i, sigcontext + reg_offset[i]);
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H A D | amd64-nat.c | 54 int *reg_offset = amd64_native_gregset64_reg_offset; local 61 reg_offset = amd64_native_gregset32_reg_offset; 71 return reg_offset[regnum];
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/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_ni_dma.c | 197 u32 reg_offset, wb_offset; local 203 reg_offset = DMA0_REGISTER_OFFSET; 207 reg_offset = DMA1_REGISTER_OFFSET; 211 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); 212 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); 220 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); 223 WREG32(DMA_RB_RPTR + reg_offset, 0); 224 WREG32(DMA_RB_WPTR + reg_offset, 0); 227 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, 229 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, [all...] |
/netbsd-current/external/gpl3/gcc.old/dist/libgcc/config/mips/ |
H A D | linux-unwind.h | 51 _Unwind_Ptr new_cfa, reg_offset; local 100 reg_offset = 4; 102 reg_offset = 0; 108 = (_Unwind_Ptr)&(sc->sc_regs[i]) + reg_offset - new_cfa;
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/netbsd-current/external/gpl3/gcc/dist/libgcc/config/mips/ |
H A D | linux-unwind.h | 51 _Unwind_Ptr new_cfa, reg_offset; local 100 reg_offset = 4; 102 reg_offset = 0; 108 = (_Unwind_Ptr)&(sc->sc_regs[i]) + reg_offset - new_cfa;
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/netbsd-current/sys/dev/isa/ |
H A D | nca_isa.c | 123 nca_isa_test(bus_space_tag_t iot, bus_space_handle_t ioh, bus_size_t reg_offset) argument 127 bus_space_write_1(iot, ioh, reg_offset + C80_ICR, SCI_ICMD_RST); 128 bus_space_write_1(iot, ioh, reg_offset + C80_ODR, 0); 132 if (bus_space_read_1(iot, ioh, reg_offset + C80_CSBR) != SCI_BUS_RST) { 135 __func__, bus_space_read_1(iot, ioh, reg_offset+C80_CSBR)); 137 bus_space_write_1(iot, ioh, reg_offset+C80_ICR, 0); 141 bus_space_write_1(iot, ioh, reg_offset + C80_ICR, 0); 146 bus_space_read_1(iot, ioh, reg_offset + C80_RPIR); 150 if (bus_space_read_1(iot, ioh, reg_offset + C80_BSR) & (SCI_CSR_PERR | 154 __func__, bus_space_read_1(iot, ioh, reg_offset 179 bus_size_t base_offset, reg_offset = 0; local [all...] |
/netbsd-current/external/gpl3/gdb.old/dist/sim/mips/ |
H A D | dv-tx3904tmr.c | 333 int reg_offset = 3 - (address - controller->base_address) % 4; local 352 memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1); 376 int reg_offset = 3 - (address - controller->base_address) % 4; local 382 if(reg_offset == 0) /* first byte */ 396 if(reg_offset == 1) /* second byte */ 400 else if(reg_offset == 0) /* first byte */ 408 if(reg_offset == 0) /* first byte */ 416 if(reg_offset == 1) /* second byte */ 421 else if(reg_offset == 0) /* first byte */ 429 if(reg_offset [all...] |
/netbsd-current/external/gpl3/gdb/dist/sim/mips/ |
H A D | dv-tx3904tmr.c | 335 int reg_offset = 3 - (address - controller->base_address) % 4; local 354 memcpy ((char*) dest + byte, ((char*)& register_value)+reg_offset, 1); 378 int reg_offset = 3 - (address - controller->base_address) % 4; local 384 if (reg_offset == 0) /* first byte */ 398 if (reg_offset == 1) /* second byte */ 402 else if (reg_offset == 0) /* first byte */ 410 if (reg_offset == 0) /* first byte */ 418 if (reg_offset == 1) /* second byte */ 423 else if (reg_offset == 0) /* first byte */ 431 if (reg_offset [all...] |