Searched refs:ref_and_mask (Results 1 - 11 of 11) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_sdma_v2_4.c286 u32 ref_and_mask = 0; local
289 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
291 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
298 amdgpu_ring_write(ring, ref_and_mask); /* reference */
299 amdgpu_ring_write(ring, ref_and_mask); /* mask */
H A Damdgpu_sdma_v3_0.c460 u32 ref_and_mask = 0; local
463 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
465 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
472 amdgpu_ring_write(ring, ref_and_mask); /* reference */
473 amdgpu_ring_write(ring, ref_and_mask); /* mask */
H A Damdgpu_cik_sdma.c256 u32 ref_and_mask; local
259 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
261 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
266 amdgpu_ring_write(ring, ref_and_mask); /* reference */
267 amdgpu_ring_write(ring, ref_and_mask); /* mask */
H A Damdgpu_sdma_v5_0.c422 u32 ref_and_mask = 0; local
426 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
428 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
435 amdgpu_ring_write(ring, ref_and_mask); /* reference */
436 amdgpu_ring_write(ring, ref_and_mask); /* mask */
H A Damdgpu_sdma_v4_0.c856 u32 ref_and_mask = 0; local
859 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
864 ref_and_mask, ref_and_mask, 10);
H A Damdgpu_gfx_v10_0.c4382 u32 ref_and_mask, reg_mem_engine; local
4388 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4391 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4398 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4405 ref_and_mask, ref_and_mask, 0x20);
H A Damdgpu_gfx_v7_0.c2141 u32 ref_and_mask; local
2147 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2150 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2156 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2165 amdgpu_ring_write(ring, ref_and_mask);
2166 amdgpu_ring_write(ring, ref_and_mask);
H A Damdgpu_gfx_v8_0.c6045 u32 ref_and_mask, reg_mem_engine; local
6051 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
6054 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
6061 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
6071 amdgpu_ring_write(ring, ref_and_mask);
6072 amdgpu_ring_write(ring, ref_and_mask);
H A Damdgpu_gfx_v9_0.c4884 u32 ref_and_mask, reg_mem_engine; local
4890 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4893 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4900 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4907 ref_and_mask, ref_and_mask, 0x20);
/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_cik_sdma.c180 u32 ref_and_mask; local
183 ref_and_mask = SDMA0;
185 ref_and_mask = SDMA1;
190 radeon_ring_write(ring, ref_and_mask); /* reference */
191 radeon_ring_write(ring, ref_and_mask); /* mask */
H A Dradeon_cik.c3525 u32 ref_and_mask; local
3533 ref_and_mask = CP2 << ring->pipe;
3536 ref_and_mask = CP6 << ring->pipe;
3543 ref_and_mask = CP0;
3553 radeon_ring_write(ring, ref_and_mask);
3554 radeon_ring_write(ring, ref_and_mask);

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