/netbsd-current/external/gpl3/gdb.old/dist/sim/mips/ |
H A D | sim-main.c | 36 starting at physical location pAddr. The data is returned in the 55 address_word pAddr, 63 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION")); 71 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) 77 pr_addr (pAddr)); 80 dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); 90 unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr); 96 value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr); 99 value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr); 102 value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr); 48 load_memory(SIM_DESC SD, sim_cpu *CPU, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD) argument 165 store_memory(SIM_DESC SD, sim_cpu *CPU, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr) argument 320 cache_op(SIM_DESC SD, sim_cpu *CPU, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction) argument [all...] |
H A D | sim-main.h | 939 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD); 940 #define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \ 941 load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD) 943 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr); 944 #define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ 945 store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr) 947 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction); 948 #define CacheOp(op,pAddr,vAddr,instruction) \ 949 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
|
/netbsd-current/external/gpl3/gdb/dist/sim/mips/ |
H A D | sim-main.c | 40 starting at physical location pAddr. The data is returned in the 59 address_word pAddr, 67 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION")); 75 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) 81 pr_addr (pAddr)); 84 dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); 94 unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr); 100 value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr); 103 value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr); 106 value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr); 52 load_memory(SIM_DESC SD, sim_cpu *CPU, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD) argument 169 store_memory(SIM_DESC SD, sim_cpu *CPU, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr) argument 324 cache_op(SIM_DESC SD, sim_cpu *CPU, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction) argument [all...] |
H A D | sim-main.h | 988 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD); 989 #define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \ 990 load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD) 992 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr); 993 #define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ 994 store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr) 996 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction); 997 #define CacheOp(op,pAddr,vAddr,instruction) \ 998 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
|
/netbsd-current/external/public-domain/sqlite/dist/ |
H A D | sqlite3.c | 71785 u8 *pAddr; local 71823 u8 *pAddr; /* The i-th cell pointer */ local [all...] |