/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
H A D | amdgpu_dcn10_mpc.c | 142 unsigned int opp_id; local 146 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); 148 if (top_sel == 0xf && opp_id == 0xf && idle) 229 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); 235 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id); 291 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, tree->opp_list->mpcc_id); 295 REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf); 362 int opp_id; local 373 for (opp_id = 0; opp_id < MAX_OP 382 int opp_id; local 402 unsigned int opp_id; local [all...] |
H A D | dcn10_hw_sequencer.h | 64 int opp_id);
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H A D | amdgpu_dcn10_hw_sequencer_debug.c | 404 if (s.opp_id != 0xf) { 406 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
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H A D | amdgpu_dcn10_hw_sequencer.c | 335 if (s.opp_id != 0xf) 337 i, s.opp_id, s.dpp_id, s.bot_mpcc_id, 1088 int opp_id = hubp->opp_id; local 1096 if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL) 1217 hubp->opp_id = OPP_ID_INVALID; 1220 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2017 int opp_id) 2217 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2562 * fairly hacky right now, using opp_id a 2013 dcn10_program_output_csc(struct dc *dc, struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace, uint16_t *matrix, int opp_id) argument [all...] |
H A D | amdgpu_dcn10_hubp.c | 71 hubp->opp_id = OPP_ID_INVALID; 1279 hubp1->base.opp_id = OPP_ID_INVALID;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
H A D | mpc.h | 116 int opp_id; /* The OPP instance that owns this MPC tree */ member in struct:mpc_tree 130 uint32_t opp_id; member in struct:mpcc_state 228 int opp_id, 233 int opp_id, 237 int opp_id, 242 int opp_id,
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H A D | hubp.h | 62 int opp_id; member in struct:hubp
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H A D | timing_generator.h | 274 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
H A D | amdgpu_dcn20_mpc.c | 81 int opp_id, 113 REG_UPDATE(DENORM_CONTROL[opp_id], 119 int opp_id, 124 REG_UPDATE_2(DENORM_CONTROL[opp_id], 127 REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], 130 REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], 139 int opp_id, 148 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); 176 ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); 177 ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); 79 mpc2_set_denorm( struct mpc *mpc, int opp_id, enum dc_color_depth output_depth) argument 117 mpc2_set_denorm_clamp( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp) argument 137 mpc2_set_output_csc( struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode) argument 191 mpc2_set_ocsc_default( struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode) argument [all...] |
H A D | amdgpu_dcn20_optc.c | 240 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, argument 264 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 279 OPTC_SEG0_SRC_SEL, opp_id[0], 280 OPTC_SEG1_SRC_SEL, opp_id[1]);
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H A D | dcn20_hwseq.h | 50 int opp_id);
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H A D | dcn20_mpc.h | 285 int opp_id, 290 int opp_id, 295 int opp_id, 301 int opp_id,
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H A D | dcn20_optc.h | 99 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
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H A D | amdgpu_dcn20_hwseq.c | 716 int opp_id) 728 opp_id, 734 opp_id, 1431 hubp->opp_id); 2211 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2344 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2363 hubp->opp_id = OPP_ID_INVALID; 2369 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 712 dcn20_program_output_csc(struct dc *dc, struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace, uint16_t *matrix, int opp_id) argument
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H A D | amdgpu_dcn20_hubp.c | 939 hubp->opp_id = OPP_ID_INVALID; 1603 hubp2->base.opp_id = OPP_ID_INVALID;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
H A D | hw_sequencer.h | 141 uint16_t *matrix, int opp_id);
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
H A D | amdgpu_dc_resource.c | 1941 if (s.opp_id < MAX_OPP) 1942 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
H A D | amdgpu_dcn21_hubp.c | 961 hubp21->base.opp_id = OPP_ID_INVALID;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
H A D | amdgpu_dce110_hw_sequencer.c | 2658 int opp_id) 2654 program_output_csc(struct dc *dc, struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace, uint16_t *matrix, int opp_id) argument
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