Searched refs:mmUVD_SYS_INT_EN (Results 1 - 4 of 4) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h334 #define mmUVD_SYS_INT_EN 0x0541 macro
H A Dvcn_2_0_0_offset.h542 #define mmUVD_SYS_INT_EN 0x0201 macro
H A Dvcn_2_5_offset.h537 #define mmUVD_SYS_INT_EN 0x00a2 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vcn_v1_0.c898 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
1061 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN,

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