Searched refs:mmUVD_RB_WPTR2 (Results 1 - 10 of 10) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_6_0_d.h | 45 #define mmUVD_RB_WPTR2 0x3c25 macro
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| H A D | uvd_7_0_offset.h | 94 #define mmUVD_RB_WPTR2 0x0425 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 216 #define mmUVD_RB_WPTR2 0x0425 macro
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| H A D | vcn_2_0_0_offset.h | 928 #define mmUVD_RB_WPTR2 0x05e5 macro
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| H A D | vcn_2_5_offset.h | 571 #define mmUVD_RB_WPTR2 0x00b3 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_vcn_v1_0.c | 949 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1176 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1255 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1605 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1623 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
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| H A D | amdgpu_vcn_v2_0.c | 1034 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1055 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1181 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1494 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1521 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
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| H A D | amdgpu_vcn_v2_5.c | 1065 WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1285 tmp = RREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR2);
1411 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1551 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
1578 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
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| H A D | amdgpu_uvd_v6_0.c | 133 return RREG32(mmUVD_RB_WPTR2);
165 WREG32(mmUVD_RB_WPTR2,
855 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
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| H A D | amdgpu_uvd_v7_0.c | 133 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
172 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
1109 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
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