Searched refs:mmUVD_RB_BASE_HI (Results 1 - 10 of 10) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_6_0_d.h | 47 #define mmUVD_RB_BASE_HI 0x3c27 macro
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| H A D | uvd_7_0_offset.h | 98 #define mmUVD_RB_BASE_HI 0x0427 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 220 #define mmUVD_RB_BASE_HI 0x0427 macro
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| H A D | vcn_2_0_0_offset.h | 932 #define mmUVD_RB_BASE_HI 0x05e7 macro
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| H A D | vcn_2_5_offset.h | 555 #define mmUVD_RB_BASE_HI 0x00ab macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_vcn_v2_5.c | 1060 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1232 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
1401 WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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| H A D | amdgpu_vcn_v1_0.c | 944 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1245 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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| H A D | amdgpu_vcn_v2_0.c | 1029 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1171 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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| H A D | amdgpu_uvd_v7_0.c | 909 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
1104 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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| H A D | amdgpu_uvd_v6_0.c | 850 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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