Searched refs:mmUVD_LMI_JRBC_RB_VMID (Results 1 - 7 of 7) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h262 #define mmUVD_LMI_JRBC_RB_VMID 0x0508 macro
H A Dvcn_2_0_0_offset.h220 #define mmUVD_LMI_JRBC_RB_VMID 0x0150 macro
H A Dvcn_2_5_offset.h235 #define mmUVD_LMI_JRBC_RB_VMID 0x0150 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_jpeg_v2_5.c340 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
H A Damdgpu_jpeg_v1_0.c524 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
H A Damdgpu_jpeg_v2_0.c363 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
H A Damdgpu_vcn_v1_0.c1305 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);

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