Searched refs:mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH (Results 1 - 4 of 4) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h274 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x050f macro
H A Dvcn_2_0_0_offset.h258 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b macro
H A Dvcn_2_5_offset.h273 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_jpeg_v1_0.c240 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));

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