Searched refs:mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW (Results 1 - 8 of 8) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_offset.h126 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0503 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h252 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0503 macro
H A Dvcn_2_0_0_offset.h248 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166 macro
H A Dvcn_2_5_offset.h263 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_jpeg_v2_5.c342 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
H A Damdgpu_jpeg_v1_0.c527 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
H A Damdgpu_jpeg_v2_0.c365 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
H A Damdgpu_vcn_v1_0.c1309 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,

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