Searched refs:mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX (Results 1 - 3 of 3) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h283 #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 macro
H A Dvcn_2_0_0_offset.h135 #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 macro
H A Dvcn_2_5_offset.h150 #define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 macro

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