Searched refs:mmUVD_DPG_LMA_MASK (Results 1 - 4 of 4) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vcn.h71 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h42 #define mmUVD_DPG_LMA_MASK 0x00d3 macro
H A Dvcn_2_0_0_offset.h400 #define mmUVD_DPG_LMA_MASK 0x0013 macro
H A Dvcn_2_5_offset.h415 #define mmUVD_DPG_LMA_MASK 0x0013 macro

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