Searched refs:mmSDMA1_RLC0_RB_WPTR_POLL_CNTL (Results 1 - 10 of 10) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma1/ |
| H A D | sdma1_4_0_offset.h | 386 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 macro
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| H A D | sdma1_4_2_2_offset.h | 386 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0137 macro
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| H A D | sdma1_4_2_offset.h | 382 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 330 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 macro
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| H A D | oss_2_0_d.h | 366 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 macro
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| H A D | oss_3_0_1_d.h | 431 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 macro
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| H A D | oss_3_0_d.h | 532 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_sdma_v4_0.c | 115 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
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| H A D | amdgpu_sdma_v5_0.c | 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 1382 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0747 macro
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