Searched refs:mmSDMA1_PAGE_RB_WPTR_POLL_CNTL (Results 1 - 6 of 6) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma1/ |
| H A D | sdma1_4_0_offset.h | 302 #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 macro
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| H A D | sdma1_4_2_2_offset.h | 302 #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00df macro
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| H A D | sdma1_4_2_offset.h | 298 #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_sdma_v4_0.c | 112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| H A D | amdgpu_sdma_v5_0.c | 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 1299 #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x06e7 macro
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