Searched refs:mmSDMA0_STATUS_REG (Results 1 - 15 of 15) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 88 #define mmSDMA0_STATUS_REG 0x0025 macro
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| H A D | sdma0_4_0_offset.h | 90 #define mmSDMA0_STATUS_REG 0x0025 macro
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| H A D | sdma0_4_2_2_offset.h | 90 #define mmSDMA0_STATUS_REG 0x0025 macro
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| H A D | sdma0_4_2_offset.h | 90 #define mmSDMA0_STATUS_REG 0x0025 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 171 #define mmSDMA0_STATUS_REG 0x340d macro
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| H A D | oss_2_0_d.h | 234 #define mmSDMA0_STATUS_REG 0x340d macro
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| H A D | oss_3_0_1_d.h | 168 #define mmSDMA0_STATUS_REG 0x340d macro
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| H A D | oss_3_0_d.h | 305 #define mmSDMA0_STATUS_REG 0x340d macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_sdma_v5_0.c | 1312 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1328 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1329 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
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| H A D | amdgpu_vi.c | 489 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
490 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
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| H A D | amdgpu_nv.c | 199 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
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| H A D | amdgpu_sdma_v4_0.c | 1970 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
1987 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
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| H A D | amdgpu_cik.c | 983 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
984 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
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| H A D | amdgpu_soc15.c | 347 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 62 #define mmSDMA0_STATUS_REG 0x0025 macro
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