Searched refs:mmSDMA0_RLC2_RB_WPTR_POLL_CNTL (Results 1 - 5 of 5) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_2_2_offset.h | 562 #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x01e7 macro
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| H A D | sdma0_4_2_offset.h | 558 #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x0207 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_sdma_v5_0.c | 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| H A D | amdgpu_sdma_v4_0.c | 172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 549 #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x0207 macro
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