Searched refs:mmSDMA0_RLC0_RB_BASE (Results 1 - 14 of 14) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_amdkfd_arcturus.c186 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
H A Damdgpu_amdkfd_gfx_v10.c484 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
H A Damdgpu_amdkfd_gfx_v8.c351 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
H A Damdgpu_amdkfd_gfx_v9.c472 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
H A Damdgpu_amdkfd_gfx_v7.c365 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h294 #define mmSDMA0_RLC0_RB_BASE 0x0141 macro
H A Dsdma0_4_0_offset.h382 #define mmSDMA0_RLC0_RB_BASE 0x0141 macro
H A Dsdma0_4_2_2_offset.h382 #define mmSDMA0_RLC0_RB_BASE 0x0131 macro
H A Dsdma0_4_2_offset.h378 #define mmSDMA0_RLC0_RB_BASE 0x0141 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h217 #define mmSDMA0_RLC0_RB_BASE 0x3501 macro
H A Doss_2_0_d.h271 #define mmSDMA0_RLC0_RB_BASE 0x3501 macro
H A Doss_3_0_1_d.h256 #define mmSDMA0_RLC0_RB_BASE 0x3501 macro
H A Doss_3_0_d.h378 #define mmSDMA0_RLC0_RB_BASE 0x3501 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h371 #define mmSDMA0_RLC0_RB_BASE 0x0141 macro
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