Searched refs:mmSDMA0_PHASE0_QUANTUM (Results 1 - 13 of 13) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h102 #define mmSDMA0_PHASE0_QUANTUM 0x002c macro
H A Dsdma0_4_0_offset.h104 #define mmSDMA0_PHASE0_QUANTUM 0x002c macro
H A Dsdma0_4_2_2_offset.h104 #define mmSDMA0_PHASE0_QUANTUM 0x002c macro
H A Dsdma0_4_2_offset.h104 #define mmSDMA0_PHASE0_QUANTUM 0x002c macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h178 #define mmSDMA0_PHASE0_QUANTUM 0x3414 macro
H A Doss_2_0_d.h241 #define mmSDMA0_PHASE0_QUANTUM 0x3414 macro
H A Doss_3_0_1_d.h176 #define mmSDMA0_PHASE0_QUANTUM 0x3414 macro
H A Doss_3_0_d.h313 #define mmSDMA0_PHASE0_QUANTUM 0x3414 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_cik_sdma.c387 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
H A Damdgpu_sdma_v3_0.c599 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
H A Damdgpu_sdma_v5_0.c571 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
H A Damdgpu_sdma_v4_0.c1028 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h76 #define mmSDMA0_PHASE0_QUANTUM 0x002c macro
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