Searched refs:mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO (Results 1 - 12 of 12) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h266 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 macro
H A Dsdma0_4_0_offset.h270 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 macro
H A Dsdma0_4_2_2_offset.h270 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 macro
H A Dsdma0_4_2_offset.h266 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h196 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 macro
H A Doss_2_0_d.h255 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 macro
H A Doss_3_0_1_d.h223 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 macro
H A Doss_3_0_d.h348 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_sdma_v3_0.c724 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
H A Damdgpu_sdma_v5_0.c654 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
H A Damdgpu_sdma_v4_0.c1146 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h260 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 macro
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