Searched refs:mmSDMA0_GFX_RB_WPTR_HI (Results 1 - 7 of 7) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h218 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
H A Dsdma0_4_0_offset.h222 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
H A Dsdma0_4_2_2_offset.h222 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
H A Dsdma0_4_2_offset.h218 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_sdma_v5_0.c310 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
358 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
650 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
684 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
H A Damdgpu_sdma_v4_0.c676 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
723 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
1109 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h213 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
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