Searched refs:mmSDMA0_GFX_IB_CNTL (Results 1 - 15 of 15) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_sdma_v3_0.c | 90 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
109 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
128 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
142 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
156 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
176 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
534 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
536 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
746 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
752 WREG32(mmSDMA0_GFX_IB_CNTL
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| H A D | amdgpu_sdma_v2_4.c | 360 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
362 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
478 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
484 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
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| H A D | amdgpu_mxgpu_vi.c | 111 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
250 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
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| H A D | amdgpu_sdma_v4_0.c | 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
930 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
932 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1160 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1166 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
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| H A D | amdgpu_sdma_v5_0.c | 508 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
510 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
741 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
747 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
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| H A D | amdgpu_cik_sdma.c | 326 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
504 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 226 #define mmSDMA0_GFX_IB_CNTL 0x008a macro
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| H A D | sdma0_4_0_offset.h | 230 #define mmSDMA0_GFX_IB_CNTL 0x008a macro
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| H A D | sdma0_4_2_2_offset.h | 230 #define mmSDMA0_GFX_IB_CNTL 0x008a macro
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| H A D | sdma0_4_2_offset.h | 226 #define mmSDMA0_GFX_IB_CNTL 0x008a macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 199 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
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| H A D | oss_2_0_d.h | 258 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
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| H A D | oss_3_0_1_d.h | 226 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
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| H A D | oss_3_0_d.h | 351 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 221 #define mmSDMA0_GFX_IB_CNTL 0x008a macro
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