Searched refs:mmRLC_EDC_CNT (Results 1 - 2 of 2) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_gfx_v9_4.c | 94 { SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT), 0, 1, 1 },
517 { "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
520 { "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
523 { "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
526 { "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
529 { "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
532 { "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
535 { "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
538 { "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_1_offset.h | 261 #define mmRLC_EDC_CNT 0x4d40 macro
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