Searched refs:mmMP0_SMN_IH_SW_INT (Results 1 - 4 of 4) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mp/
H A Dmp_10_0_offset.h176 #define mmMP0_SMN_IH_SW_INT 0x00c2 macro
H A Dmp_11_0_offset.h178 #define mmMP0_SMN_IH_SW_INT 0x00c2 macro
H A Dmp_12_0_0_offset.h176 #define mmMP0_SMN_IH_SW_INT 0x00c2 macro
H A Dmp_9_0_offset.h178 #define mmMP0_SMN_IH_SW_INT 0x00c2 macro

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