Searched refs:mmJPEG_CGC_CTRL (Results 1 - 7 of 7) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_jpeg_v2_5.c | 262 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
270 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
280 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
285 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
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| H A D | amdgpu_jpeg_v2_0.c | 287 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
295 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
310 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
318 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
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| H A D | amdgpu_vcn_v1_0.c | 449 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
458 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
576 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
583 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
647 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_7_0_offset.h | 156 #define mmJPEG_CGC_CTRL 0x0565 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 336 #define mmJPEG_CGC_CTRL 0x0565 macro
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| H A D | vcn_2_0_0_offset.h | 352 #define mmJPEG_CGC_CTRL 0x01e1 macro
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| H A D | vcn_2_5_offset.h | 367 #define mmJPEG_CGC_CTRL 0x01e1 macro
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