Searched refs:mmATC_L2_CACHE_4K_DSM_CNTL (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h238 #define mmATC_L2_CACHE_4K_DSM_CNTL 0x0810 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx_v9_4.c794 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);
953 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);

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