| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | amdgpu_dcn10_hw_sequencer_debug.c | 128 "min_ttu_vblank,qos_low_wm,qos_high_wm"
132 "min_ttu_vblank,qos_low_wm,qos_high_wm"
161 (s->min_ttu_vblank * frac) / ref_clk_mhz / frac, (s->min_ttu_vblank * frac) / ref_clk_mhz % frac,
181 (s->min_ttu_vblank * frac) / ref_clk_mhz / frac, (s->min_ttu_vblank * frac) / ref_clk_mhz % frac,
316 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
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| H A D | amdgpu_dcn10_hubp.c | 720 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
967 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
1024 MIN_TTU_VBLANK, &s->min_ttu_vblank);
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| H A D | dcn10_hubp.h | 678 uint32_t min_ttu_vblank; member in struct:dcn_hubp_state
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| H A D | amdgpu_dcn10_hw_sequencer.c | 166 "HUBP: format addr_hi width height rot mir sw_mode dcc_en blank_en clock_en ttu_dis underflow min_ttu_vblank qos_low_wm qos_high_wm\n");
188 DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
262 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
1698 "min_ttu_vblank: %d, \n"
1712 pipe_ctx->ttu_regs.min_ttu_vblank,
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| H A D | amdgpu_dml1_display_rq_dlg_calc.c | 1013 double min_ttu_vblank; local
1152 min_ttu_vblank = dlg_sys_param.t_urg_wm_us;
1154 min_ttu_vblank = dml_max(dlg_sys_param.t_sr_wm_us, min_ttu_vblank);
1156 min_ttu_vblank = dml_max(dlg_sys_param.t_mclk_wm_us, min_ttu_vblank);
1157 min_ttu_vblank = min_ttu_vblank + t_calc_us;
1159 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
1167 DTRACE("DLG: %s: min_ttu_vblank
[all...] |
| H A D | amdgpu_display_rq_dlg_helpers.c | 347 "DML_RQ_DLG_CALC: min_ttu_vblank = 0x%0x\n",
348 ttu_regs.min_ttu_vblank);
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| H A D | display_mode_structs.h | 474 unsigned int min_ttu_vblank; member in struct:_vcs_dpi_display_ttu_regs_st
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| H A D | display_mode_vba.h | 67 dml_get_pipe_attr_decl(min_ttu_vblank); variable
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| H A D | amdgpu_display_mode_vba.c | 126 dml_get_pipe_attr_func(min_ttu_vblank, mode_lib->vba.MinTTUVBlank);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| H A D | amdgpu_display_rq_dlg_calc_20.c | 810 double min_ttu_vblank; local
932 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
934 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
943 dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n",
945 min_ttu_vblank);
1560 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1561 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
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| H A D | amdgpu_display_rq_dlg_calc_20v2.c | 810 double min_ttu_vblank; local
932 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
934 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
944 dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n",
946 min_ttu_vblank);
1561 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1562 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| H A D | amdgpu_display_rq_dlg_calc_21.c | 856 double min_ttu_vblank; local
978 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
980 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
991 "DML_DLG: %s: min_ttu_vblank = %3.2f\n",
993 min_ttu_vblank);
1660 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1661 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_hubp.c | 294 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
1159 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
1216 MIN_TTU_VBLANK, &s->min_ttu_vblank);
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| H A D | amdgpu_dcn20_hwseq.c | 1280 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1298 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
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