Searched refs:meta_req_width (Results 1 - 6 of 6) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
H A Damdgpu_display_rq_dlg_calc_20.c361 unsigned int meta_req_width; local
482 meta_req_width = 1 << log2_meta_req_width;
491 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
492 + meta_req_width;
493 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
542 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
H A Damdgpu_display_rq_dlg_calc_20v2.c361 unsigned int meta_req_width; local
482 meta_req_width = 1 << log2_meta_req_width;
491 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
492 + meta_req_width;
493 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
542 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
H A Damdgpu_display_rq_dlg_calc_21.c351 unsigned int meta_req_width; local
476 meta_req_width = 1 << log2_meta_req_width;
485 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
486 + meta_req_width;
487 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
539 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
H A Damdgpu_display_mode_vba_21.c442 unsigned int meta_req_width[],
1965 &locals->meta_req_width[k],
2528 locals->meta_req_width,
4556 &locals->meta_req_width[k],
5844 unsigned int meta_req_width[],
5919 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
5821 CalculateMetaAndPTETimes( unsigned int NumberOfActivePlanes, bool GPUVMEnable, unsigned int MetaChunkSize, unsigned int MinMetaChunkSizeBytes, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], double VRatio[], double VRatioPrefetchY[], double VRatioPrefetchC[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], double BytePerPixelDETY[], double BytePerPixelDETC[], enum scan_direction_class SourceScan[], unsigned int dpte_row_height[], unsigned int dpte_row_height_chroma[], unsigned int meta_row_width[], unsigned int meta_row_height[], unsigned int meta_req_width[], unsigned int meta_req_height[], int dpte_group_bytes[], unsigned int PTERequestSizeY[], unsigned int PTERequestSizeC[], unsigned int PixelPTEReqWidthY[], unsigned int PixelPTEReqHeightY[], unsigned int PixelPTEReqWidthC[], unsigned int PixelPTEReqHeightC[], unsigned int dpte_row_width_luma_ub[], unsigned int dpte_row_width_chroma_ub[], unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], unsigned int meta_pte_bytes_per_frame_ub_l[], unsigned int meta_pte_bytes_per_frame_ub_c[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], double TimePerMetaChunkNominal[], double TimePerMetaChunkVBlank[], double TimePerMetaChunkFlip[], double time_per_pte_group_nom_luma[], double time_per_pte_group_vblank_luma[], double time_per_pte_group_flip_luma[], double time_per_pte_group_nom_chroma[], double time_per_pte_group_vblank_chroma[], double time_per_pte_group_flip_chroma[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], double TimePerVMRequestFlip[]) argument
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
H A Damdgpu_dml1_display_rq_dlg_calc.c570 unsigned int meta_req_width; local
713 meta_req_width = 1 << log2_meta_req_width;
723 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
724 + meta_req_width;
725 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
769 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
H A Ddisplay_mode_vba.h588 unsigned int meta_req_width[DC__NUM_DPP__MAX]; member in struct:vba_vars_st

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