Searched refs:ixCG_SPLL_FUNC_CNTL_2 (Results 1 - 10 of 10) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| H A D | amdgpu_ci_baco.c | 71 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
75 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
80 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
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| H A D | amdgpu_fiji_baco.c | 69 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
73 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
78 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
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| H A D | amdgpu_tonga_baco.c | 69 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
73 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
78 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_SPLL_FUNC_CNTL_2 },
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| H A D | amdgpu_smu7_hwmgr.c | 4290 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/ |
| H A D | smu_7_0_0_d.h | 48 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
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| H A D | smu_7_1_3_d.h | 51 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
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| H A D | smu_7_1_2_d.h | 48 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
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| H A D | smu_7_1_0_d.h | 48 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
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| H A D | smu_7_0_1_d.h | 48 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
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| H A D | smu_7_1_1_d.h | 48 #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 macro
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