Searched refs:isSGPRClass (Results 1 - 12 of 12) sorted by relevance

/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h154 bool isSGPRClass(const TargetRegisterClass *RC) const { function in class:llvm::final
160 return isSGPRClass(getRegClass(RCID));
238 return !isSGPRClass(RC);
H A DSIFixSGPRCopies.cpp164 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) &&
171 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) &&
223 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
269 assert(TRI->isSGPRClass(SrcRC) &&
688 if (TRI->isSGPRClass(DstRC) &&
814 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass &&
842 if (TRI->isSGPRClass(RC))
H A DSIInstrInfo.cpp862 if (RC == RI.getVGPR64Class() && (SrcRC == RC || RI.isSGPRClass(SrcRC))) {
880 if (RI.isSGPRClass(RC)) {
881 if (!RI.isSGPRClass(SrcRC)) {
898 (SrcRC == RC || RI.isSGPRClass(SrcRC)))) {
1019 if (RI.isSGPRClass(RegClass)) {
1201 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1202 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
1204 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
1422 if (RI.isSGPRClass(RC)) {
1555 if (RI.isSGPRClass(R
[all...]
H A DGCNRegPressure.cpp77 return STI->isSGPRClass(RC) ?
H A DGCNHazardRecognizer.cpp977 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) {
1058 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg())))
H A DSIRegisterInfo.cpp2074 return isSGPRClass(RC);
2138 if (isSGPRClass(RC)) {
H A DAMDGPUTargetTransformInfo.cpp947 if (!RC || !TRI->isSGPRClass(RC))
H A DSIFoldOperands.cpp696 if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) {
H A DSIISelLowering.cpp3710 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) {
3814 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) {
12186 if (!TRI->isSGPRClass(RC) && !isDivergent)
12188 else if (TRI->isSGPRClass(RC) && isDivergent)
12269 else if (SIRI->isSGPRClass(RC))
H A DAMDGPUISelDAGToDAG.cpp2950 if (!RC || SIRI->isSGPRClass(RC))
H A DAMDGPURegisterBankInfo.cpp283 if (TRI->isSGPRClass(&RC)) {
H A DAMDGPUInstructionSelector.cpp157 TRI.isSGPRClass(SrcRC) ? AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32;

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