Searched refs:h_gr (Results 1 - 25 of 47) sorted by relevance

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/netbsd-current/external/gpl3/gdb.old/dist/sim/lm32/
H A Dsem-switch.c311 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
312 CPU (h_gr[FLD (f_r2)]) = opval;
330 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
331 CPU (h_gr[FLD (f_r1)]) = opval;
349 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
350 CPU (h_gr[FLD (f_r2)]) = opval;
368 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
369 CPU (h_gr[FL
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H A Dsem.c211 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
212 CPU (h_gr[FLD (f_r2)]) = opval;
232 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
233 CPU (h_gr[FLD (f_r1)]) = opval;
253 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
254 CPU (h_gr[FLD (f_r2)]) = opval;
274 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
275 CPU (h_gr[FL
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H A Dcpu.c51 return CPU (h_gr[regno]);
59 CPU (h_gr[regno]) = newval;
/netbsd-current/external/gpl3/gdb/dist/sim/lm32/
H A Dcpu.c51 return CPU (h_gr[regno]);
59 CPU (h_gr[regno]) = newval;
H A Dsem-switch.c311 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
312 CPU (h_gr[FLD (f_r2)]) = opval;
330 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
331 CPU (h_gr[FLD (f_r1)]) = opval;
349 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
350 CPU (h_gr[FLD (f_r2)]) = opval;
368 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
369 CPU (h_gr[FL
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H A Dsem.c211 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
212 CPU (h_gr[FLD (f_r2)]) = opval;
232 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
233 CPU (h_gr[FLD (f_r1)]) = opval;
253 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
254 CPU (h_gr[FLD (f_r2)]) = opval;
274 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm)));
275 CPU (h_gr[FL
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/netbsd-current/external/gpl3/gdb.old/dist/sim/sh64/
H A Dcpu.h55 DI h_gr[64]; member in struct:__anon3141::__anon3142
56 #define GET_H_GR(index) ((((index) == (63))) ? (MAKEDI (0, 0)) : (CPU (h_gr[index])))
60 CPU (h_gr[(index)]) = (x);\
131 #define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
134 CPU (h_gr[(index)]) = EXTSIDI ((x));\
219 #define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
222 CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
224 #define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1)
227 CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\
229 #define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UIN
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/netbsd-current/external/gpl3/gdb.old/dist/sim/m32r/
H A Dm32rx.c62 return CPU (h_gr[H_GR_SP]);
67 return CPU (h_gr[H_GR_SP]);
100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
120 CPU (h_gr[H_GR_SP]) = newval;
126 CPU (h_gr[H_GR_SP]) = newval;
235 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
238 && (h_gr
233 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local
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H A Dm32r2.c62 return CPU (h_gr[H_GR_SP]);
67 return CPU (h_gr[H_GR_SP]);
100 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
101 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
106 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
107 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
120 CPU (h_gr[H_GR_SP]) = newval;
126 CPU (h_gr[H_GR_SP]) = newval;
235 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
238 && (h_gr
233 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local
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H A Dm32r.c143 return CPU (h_gr[H_GR_SP]);
148 return CPU (h_gr[H_GR_SP]);
181 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
182 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
187 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
188 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
201 CPU (h_gr[H_GR_SP]) = newval;
207 CPU (h_gr[H_GR_SP]) = newval;
328 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
331 && (h_gr
326 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local
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H A Ddecode.c600 FLD (i_dr) = & CPU (h_gr)[f_r1];
601 FLD (i_sr) = & CPU (h_gr)[f_r2];
634 FLD (i_sr) = & CPU (h_gr)[f_r2];
635 FLD (i_dr) = & CPU (h_gr)[f_r1];
667 FLD (i_sr) = & CPU (h_gr)[f_r2];
668 FLD (i_dr) = & CPU (h_gr)[f_r1];
700 FLD (i_sr) = & CPU (h_gr)[f_r2];
701 FLD (i_dr) = & CPU (h_gr)[f_r1];
730 FLD (i_dr) = & CPU (h_gr)[f_r1];
759 FLD (i_dr) = & CPU (h_gr)[f_r
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H A Dcpux.c51 return CPU (h_gr[regno]);
59 CPU (h_gr[regno]) = newval;
H A Dcpu2.c51 return CPU (h_gr[regno]);
59 CPU (h_gr[regno]) = newval;
H A Dcpu.c51 return CPU (h_gr[regno]);
59 CPU (h_gr[regno]) = newval;
H A Ddecode2.c789 FLD (i_dr) = & CPU (h_gr)[f_r1];
790 FLD (i_sr) = & CPU (h_gr)[f_r2];
823 FLD (i_sr) = & CPU (h_gr)[f_r2];
824 FLD (i_dr) = & CPU (h_gr)[f_r1];
856 FLD (i_sr) = & CPU (h_gr)[f_r2];
857 FLD (i_dr) = & CPU (h_gr)[f_r1];
889 FLD (i_sr) = & CPU (h_gr)[f_r2];
890 FLD (i_dr) = & CPU (h_gr)[f_r1];
919 FLD (i_dr) = & CPU (h_gr)[f_r1];
948 FLD (i_dr) = & CPU (h_gr)[f_r
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H A Ddecodex.c730 FLD (i_dr) = & CPU (h_gr)[f_r1];
731 FLD (i_sr) = & CPU (h_gr)[f_r2];
764 FLD (i_sr) = & CPU (h_gr)[f_r2];
765 FLD (i_dr) = & CPU (h_gr)[f_r1];
797 FLD (i_sr) = & CPU (h_gr)[f_r2];
798 FLD (i_dr) = & CPU (h_gr)[f_r1];
830 FLD (i_sr) = & CPU (h_gr)[f_r2];
831 FLD (i_dr) = & CPU (h_gr)[f_r1];
860 FLD (i_dr) = & CPU (h_gr)[f_r1];
889 FLD (i_dr) = & CPU (h_gr)[f_r
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/netbsd-current/external/gpl3/gdb/dist/sim/m32r/
H A Dm32r2.c65 return CPU (h_gr[H_GR_SP]);
70 return CPU (h_gr[H_GR_SP]);
103 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
104 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
109 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
110 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
123 CPU (h_gr[H_GR_SP]) = newval;
129 CPU (h_gr[H_GR_SP]) = newval;
238 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
241 && (h_gr
236 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local
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H A Dm32rx.c65 return CPU (h_gr[H_GR_SP]);
70 return CPU (h_gr[H_GR_SP]);
103 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
104 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
109 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
110 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
123 CPU (h_gr[H_GR_SP]) = newval;
129 CPU (h_gr[H_GR_SP]) = newval;
238 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
241 && (h_gr
236 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local
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H A Dm32r.c163 return CPU (h_gr[H_GR_SP]);
168 return CPU (h_gr[H_GR_SP]);
201 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
202 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
207 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
208 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
221 CPU (h_gr[H_GR_SP]) = newval;
227 CPU (h_gr[H_GR_SP]) = newval;
348 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
351 && (h_gr
346 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; local
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H A Ddecode.c600 FLD (i_dr) = & CPU (h_gr)[f_r1];
601 FLD (i_sr) = & CPU (h_gr)[f_r2];
634 FLD (i_sr) = & CPU (h_gr)[f_r2];
635 FLD (i_dr) = & CPU (h_gr)[f_r1];
667 FLD (i_sr) = & CPU (h_gr)[f_r2];
668 FLD (i_dr) = & CPU (h_gr)[f_r1];
700 FLD (i_sr) = & CPU (h_gr)[f_r2];
701 FLD (i_dr) = & CPU (h_gr)[f_r1];
730 FLD (i_dr) = & CPU (h_gr)[f_r1];
759 FLD (i_dr) = & CPU (h_gr)[f_r
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H A Dcpux.c51 return CPU (h_gr[regno]);
59 CPU (h_gr[regno]) = newval;
H A Dcpu2.c51 return CPU (h_gr[regno]);
59 CPU (h_gr[regno]) = newval;
H A Dcpu.c51 return CPU (h_gr[regno]);
59 CPU (h_gr[regno]) = newval;
H A Ddecode2.c789 FLD (i_dr) = & CPU (h_gr)[f_r1];
790 FLD (i_sr) = & CPU (h_gr)[f_r2];
823 FLD (i_sr) = & CPU (h_gr)[f_r2];
824 FLD (i_dr) = & CPU (h_gr)[f_r1];
856 FLD (i_sr) = & CPU (h_gr)[f_r2];
857 FLD (i_dr) = & CPU (h_gr)[f_r1];
889 FLD (i_sr) = & CPU (h_gr)[f_r2];
890 FLD (i_dr) = & CPU (h_gr)[f_r1];
919 FLD (i_dr) = & CPU (h_gr)[f_r1];
948 FLD (i_dr) = & CPU (h_gr)[f_r
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H A Ddecodex.c730 FLD (i_dr) = & CPU (h_gr)[f_r1];
731 FLD (i_sr) = & CPU (h_gr)[f_r2];
764 FLD (i_sr) = & CPU (h_gr)[f_r2];
765 FLD (i_dr) = & CPU (h_gr)[f_r1];
797 FLD (i_sr) = & CPU (h_gr)[f_r2];
798 FLD (i_dr) = & CPU (h_gr)[f_r1];
830 FLD (i_sr) = & CPU (h_gr)[f_r2];
831 FLD (i_dr) = & CPU (h_gr)[f_r1];
860 FLD (i_dr) = & CPU (h_gr)[f_r1];
889 FLD (i_dr) = & CPU (h_gr)[f_r
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