Searched refs:gmbus (Results 1 - 4 of 4) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Dedid.c136 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
165 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
213 i2c_edid->gmbus.total_byte_count =
217 /* vgpu gmbus only support EDID */
222 "vgpu%d: unsupported gmbus slave addr(0x%x)\n"
223 " gmbus operations will be ignored.\n",
231 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
249 * visible in gmbus interface)
251 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
263 i2c_edid->gmbus
[all...]
H A Dedid.h139 struct intel_vgpu_i2c_gmbus gmbus; member in struct:intel_vgpu_i2c_edid
/netbsd-current/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_gmbus.c53 /* Map gmbus pin pairs to names and registers. */
621 * The gmbus controller can combine a 1 or 2 byte write with another read/write
708 /* Generate a STOP condition on the bus. Note that gmbus can't generata
710 * unconditionally generate the STOP condition with an additional gmbus
737 * from retrying. So return -ENXIO only when gmbus properly quiescents -
935 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
939 bus = &dev_priv->gmbus[pin];
945 "i915 gmbus %s",
963 /* gmbus seems to be broken on i830 */
983 bus = &dev_priv->gmbus[pi
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_drv.h950 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; member in struct:drm_i915_private
952 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
957 * Base address of where the gmbus and gpio blocks are located (either

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