Searched refs:getDesc (Results 1 - 25 of 156) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h340 return MI.getDesc().TSFlags & SIInstrFlags::SALU;
348 return MI.getDesc().TSFlags & SIInstrFlags::VALU;
364 return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
372 return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
380 return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
388 return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
396 return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
404 return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
412 return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
420 return MI.getDesc()
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H A DSIPostRABundler.cpp107 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags;
113 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags;
117 ((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) &&
/netbsd-current/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
H A DSchedulerStatistics.cpp47 NumIssued += Inst.getDesc().NumMicroOps;
51 if (LQResourceID && Inst.getDesc().MayLoad &&
56 if (SQResourceID && Inst.getDesc().MayStore &&
63 if (LQResourceID && Inst.getDesc().MayLoad) {
67 if (SQResourceID && Inst.getDesc().MayStore) {
H A DRetireControlUnitStatistics.cpp39 unsigned ReleasedEntries = Event.IR.getInstruction()->getDesc().NumMicroOps;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp236 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
243 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
248 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, function in class:HexagonMCInstrInfo
311 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
329 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
335 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
341 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
374 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
399 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
428 int SchedClass = HexagonMCInstrInfo::getDesc(MCI
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H A DHexagonShuffler.cpp130 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad());
131 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore());
197 MCInst const &Inst = ISJ.getDesc();
229 MCInst const &Inst = ISJ.getDesc();
230 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) {
364 MCInst const &ID = ISJ->getDesc();
371 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) {
404 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) {
446 MCInst const &ID = ISJ->getDesc();
485 if (HexagonMCInstrInfo::getDesc(MCI
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H A DHexagonMCShuffler.cpp41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo());
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo());
86 MCInst const &MI = I->getDesc();
H A DHexagonMCChecker.cpp90 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI);
312 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
323 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
337 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
425 bool Branch = HexagonMCInstrInfo::getDesc(MCII, I).isBranch();
465 HexagonMCInstrInfo::getDesc(MCII, *std::get<0>(Producer));
506 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs();
523 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(),
539 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I);
564 HexagonMCInstrInfo::getDesc(MCI
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/
H A DMicroOpQueueStage.h57 IR.getInstruction()->getDesc().NumMicroOps);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrBuilder.h29 const MCInstrDesc &MCID = MI->getDesc();
/netbsd-current/external/bsd/openldap/dist/contrib/ldapc++/src/
H A DLDAPAttrType.h57 string getDesc() const;
H A DLDAPObjClass.h59 string getDesc() const;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86DiscriminateMemOps.cpp113 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode))
129 if (X86II::getMemoryOperandNo(MI.getDesc().TSFlags) < 0)
131 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode))
/netbsd-current/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp41 const InstrDesc &Desc = Inst.getDesc();
56 if (RM.checkAvailability(IR.getInstruction()->getDesc())) {
164 if (!IR.getInstruction()->getDesc().RetireOOO) {
225 const InstrDesc &Desc = IS.getDesc();
268 if (!IR.getInstruction()->getDesc().RetireOOO)
323 if (CarriedOver.getInstruction()->getDesc().EndGroup)
H A DInstructionTables.cpp23 const InstrDesc &Desc = IR.getInstruction()->getDesc();
H A DDispatchStage.cpp81 const InstrDesc &Desc = IS.getDesc();
162 const InstrDesc &Desc = Inst.getDesc();
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblySetP2AlignOperands.cpp65 assert(MI.getDesc().OpInfo[OperandNo].OperandType ==
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp29 const MCInstrDesc &MCID = MI->getDesc();
50 const MCInstrDesc &MCID = MI->getDesc();
53 const MCInstrDesc &LastMCID = LastMI->getDesc();
110 uint64_t TSFlags = MI.getDesc().TSFlags;
/netbsd-current/external/bsd/openldap/dist/contrib/ldapc++/examples/
H A DreadSchema.cpp53 std::cout << test.getDesc() << std::endl;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetSchedule.cpp110 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
135 unsigned SchedClass = MI->getDesc().getSchedClass();
198 unsigned DefClass = DefMI->getDesc().getSchedClass();
242 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
327 unsigned SchedClass = MI->getDesc().getSchedClass();
H A DExecutionDomainFix.cpp237 const MCInstrDesc &MCID = MI->getDesc();
259 for (unsigned i = mi->getDesc().getNumDefs(),
260 e = mi->getDesc().getNumOperands();
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
290 for (unsigned i = mi->getDesc().getNumDefs(),
291 e = mi->getDesc().getNumOperands();
/netbsd-current/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp74 const InstrDesc &D = IS->getDesc();
199 uint64_t BusyResourceMask = Resources->checkAvailability(IS.getDesc());
253 if (Resources->checkAvailability(IS.getDesc()))
291 const InstrDesc &Desc = IR.getInstruction()->getDesc();
H A DLSUnit.cpp70 const InstrDesc &Desc = IR.getInstruction()->getDesc();
196 const InstrDesc &Desc = IR.getInstruction()->getDesc();
214 const InstrDesc &Desc = IR.getInstruction()->getDesc();
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Support/
H A DStatistic.cpp144 return std::strcmp(LHS->getDesc(), RHS->getDesc()) < 0;
194 Stats.Stats[i]->getDesc());

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