Searched refs:gart (Results 1 - 25 of 33) sorted by relevance

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/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_gart.c67 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
73 * gart table to be in system memory.
82 error = bus_dmamem_alloc(rdev->ddev->dmat, rdev->gart.table_size,
83 PAGE_SIZE, 0, &rdev->gart.rg_table_seg, 1, &rsegs, BUS_DMA_WAITOK);
87 error = bus_dmamap_create(rdev->ddev->dmat, rdev->gart.table_size, 1,
88 rdev->gart.table_size, 0, BUS_DMA_WAITOK,
89 &rdev->gart.rg_table_map);
92 error = bus_dmamem_map(rdev->ddev->dmat, &rdev->gart.rg_table_seg, 1,
93 rdev->gart.table_size, &rdev->gart
[all...]
H A Dradeon_rs400.c50 /* Check gart size */
90 if (rdev->gart.ptr) {
94 /* Check gart size */
107 /* Initialize common gart structure */
113 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
125 /* Check gart size */
171 tmp = (u32)rdev->gart.table_addr & 0xfffff000;
172 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
194 /* Enable gart */
[all...]
H A Dradeon_asic.c157 * Removes AGP flags and changes the gart callbacks on AGP
158 * cards when using the internal gart rather than AGP (all asics).
172 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
173 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
174 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
178 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
179 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
180 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
214 .gart = {
282 .gart
[all...]
H A Dradeon_rs600.c548 if (rdev->gart.robj) {
552 /* Initialize common gart structure */
557 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
566 if (rdev->gart.robj == NULL) {
603 rdev->gart.table_addr);
620 (unsigned long long)rdev->gart.table_addr);
621 rdev->gart.ready = true;
629 /* FIXME: disable out of gart access */
674 void __iomem *ptr = (void *)rdev->gart
[all...]
H A Dradeon_r300.c147 void __iomem *ptr = rdev->gart.ptr;
164 if (rdev->gart.robj) {
168 /* Initialize common gart structure */
174 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
175 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
176 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
177 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
178 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
188 if (rdev->gart
[all...]
H A Dradeon_r100.c650 if (rdev->gart.ptr) {
654 /* Initialize common gart structure */
658 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
659 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
660 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
661 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
676 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
682 (unsigned long long)rdev->gart.table_addr);
683 rdev->gart
[all...]
H A Dradeon_ttm.c1258 if (p >= rdev->gart.num_cpu_pages)
1261 page = rdev->gart.pages[p];
1267 kunmap(rdev->gart.pages[p]);
H A Dradeon_vm.c42 * GPUVM is similar to the legacy gart on older asics, however
43 * rather than there being a single global gart table
375 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
593 * radeon_vm_map_gart - get the physical address of a gart page
607 result = rdev->gart.pages_entry[addr >> RADEON_GPU_PAGE_SHIFT];
H A Dradeon_ni.c1285 if (rdev->gart.robj == NULL) {
1314 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1360 (unsigned long long)rdev->gart.table_addr);
1361 rdev->gart.ready = true;
1417 /* flush read cache over gart for this vmid */
1460 /* flush read cache over gart for this vmid */
H A Dradeon_rv770.c907 if (rdev->gart.robj == NULL) {
936 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
947 (unsigned long long)rdev->gart.table_addr);
948 rdev->gart.ready = true;
H A Dradeon_r600.c1111 void __iomem *ptr = rdev->gart.ptr;
1150 if (rdev->gart.robj) {
1154 /* Initialize common gart structure */
1158 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
1167 if (rdev->gart.robj == NULL) {
1204 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1215 (unsigned long long)rdev->gart.table_addr);
1216 rdev->gart.ready = true;
2911 /* flush read cache over gart */
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gart.c73 * This dummy page is used by the driver as a filler for gart entries
164 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
170 * gart table to be in video memory.
177 if (adev->gart.bo == NULL) {
181 bp.size = adev->gart.table_size;
188 r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
197 * amdgpu_gart_table_vram_pin - pin gart page table in vram
203 * gart table to be in video memory.
210 r = amdgpu_bo_reserve(adev->gart.bo, false);
213 r = amdgpu_bo_pin(adev->gart
[all...]
H A Damdgpu_gmc_v10_0.c334 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
381 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
679 * vram and gart within the GPU's physical address space.
702 /* set the gart size */
724 if (adev->gart.bo) {
729 /* Initialize common gart structure */
734 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
735 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
762 be aware of gart tabl
[all...]
H A Damdgpu_gmc_v6_0.c351 /* set the gart size */
494 if (adev->gart.bo == NULL) {
502 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
580 adev->gart.ready = true;
588 if (adev->gart.bo) {
595 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
596 adev->gart.gart_pte_flags = 0;
H A Damdgpu_gmc_v7_0.c262 * Set the location of vram, gart, and AGP in the GPU's
324 * vram and gart within the GPU's physical address space (CIK).
405 /* set the gart size */
471 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
612 * gmc_v7_0_gart_enable - gart enable
628 if (adev->gart.bo == NULL) {
636 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
724 adev->gart.ready = true;
732 if (adev->gart.bo) {
736 /* Initialize common gart structur
[all...]
H A Damdgpu_gmc_v9_0.c956 * vram and gart within the GPU's physical address space.
991 /* set the gart size */
1019 if (adev->gart.bo) {
1023 /* Initialize common gart structure */
1027 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1028 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1290 * gmc_v9_0_gart_enable - gart enable
1298 if (adev->gart.bo == NULL) {
1319 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart
[all...]
H A Damdgpu_gtt_mgr.c209 lpfn = adev->gart.num_cpu_pages;
H A Damdgpu_gmc_v8_0.c453 * Set the location of vram, gart, and AGP in the GPU's
526 * vram and gart within the GPU's physical address space (VI).
606 /* set the gart size */
673 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
833 * gmc_v8_0_gart_enable - gart enable
849 if (adev->gart.bo == NULL) {
857 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
962 adev->gart.ready = true;
970 if (adev->gart.bo) {
974 /* Initialize common gart structur
[all...]
H A Damdgpu_ttm.c1593 flags |= adev->gart.gart_pte_flags;
2206 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
2270 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2545 if (p >= adev->gart.num_cpu_pages)
2548 page = adev->gart.pages[p];
2554 kunmap(adev->gart.pages[p]);
H A Damdgpu_gfxhub_v1_0.c59 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
H A Damdgpu_gfxhub_v2_0.c70 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
H A Damdgpu_mmhub_v2_0.c55 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
/netbsd-current/sys/external/bsd/drm2/dist/drm/nouveau/
H A Dnouveau_chan.h20 struct nvif_object gart; member in struct:nouveau_channel
H A Dnouveau_chan.c111 nvif_object_fini(&chan->gart);
362 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) argument
384 /* allocate dma objects to cover all allowed vram, and gart */
422 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
423 &args, sizeof(args), &chan->gart);
/netbsd-current/sys/external/bsd/drm/dist/shared-core/
H A Dxgi_drm.h52 struct drm_map gart; member in struct:xgi_bootstrap

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