/netbsd-current/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.base/ |
H A D | float128.c | 22 __float128 f128; variable 31 f128 = 2.375q;
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H A D | floatn.c | 23 _Float128 f128; variable 37 f128 = 3.375f128; 43 c128 = 3.375f128 + 1.0if;
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/netbsd-current/external/gpl3/gdb/dist/gdb/testsuite/gdb.base/ |
H A D | float128.c | 22 __float128 f128; variable 31 f128 = 2.375q;
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H A D | floatn.c | 23 _Float128 f128; variable 37 f128 = 3.375f128; 43 c128 = 3.375f128 + 1.0if;
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/netbsd-current/regress/lib/libc/ieeefp/testfloat/ |
H A D | systfloat.c | 87 float128 f128; member in union:__anon7824 140 return uz.f128; 179 return uz.f128; 236 return ub.f128; 346 return uz.f128; 518 const union128 ua = { .f128 = a }; 527 const union128 ua = { .f128 = a }; 536 const union128 ua = { .f128 = a }; 546 const union128 ua = { .f128 = a }; 555 const union128 ua = { .f128 [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 107 assert((LocVT == MVT::f32 || LocVT == MVT::f128 112 unsigned size = (LocVT == MVT::f128) ? 16 : 8; 113 Align alignment = (LocVT == MVT::f128) ? Align(16) : Align(8); 126 else if (LocVT == MVT::f128 && Offset < 16*8) 510 } else if (VA.getValVT() == MVT::f128) { 511 report_fatal_error("SPARCv8 does not handle f128 in calls; " 1052 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) 1075 assert(ValTy == MVT::f128 && "Unexpected type!"); 1156 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But 1158 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 [all...] |
H A D | SparcISelLowering.h | 186 // Do not shrink FP constpool if VT == MVT::f128. 188 return VT != MVT::f128;
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/netbsd-current/external/gpl3/gcc/dist/libgfortran/ieee/ |
H A D | ieee_helper.c | 165 VALUEMACRO(16, f128)
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/netbsd-current/external/lgpl3/mpfr/dist/src/ |
H A D | set_float128.c | 31 # define MPFR_FLOAT128_MAX 0x1.ffffffffffffffffffffffffffffp+16383f128
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 222 if (RetVT == MVT::f128) 227 if (RetVT == MVT::f128) 232 if (RetVT == MVT::f128) 237 if (RetVT == MVT::f128) 254 if (OpVT == MVT::f128) 263 if (OpVT == MVT::f128) 270 if (OpVT == MVT::f128) 275 if (OpVT == MVT::f128) 313 } else if (OpVT == MVT::f128) { 362 } else if (OpVT == MVT::f128) { [all...] |
H A D | ValueTypes.cpp | 198 case MVT::f128: return Type::getFP128Ty(Context); 517 case Type::FP128TyID: return MVT(MVT::f128);
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/netbsd-current/external/lgpl3/gmp/dist/tests/rand/ |
H A D | t-rand.c | 77 const char *f128[ENTS] = {"0.af66ba932aaf58a071fd8f0742a99a0c@0", "0.73cfa3c664c9c1753507ca60ec6b8425@0", "0.53ea074ca131dec12cd68b8aa8e20278@0", "0.3cf5ac8c343532f8a53cc0eb47581f73@0", "0.50c11d5869e208aa1b9aa317b8c2d0a9@0", "0.8b23163c892876472b1ef19642eace09@0", "0.489f4c03d41f87509c8d6c90ce674f95@0", "0.aab8748c96aa6762ea1932b44c9d7164@0", "0.98cb5591fc05ad31afbbc1d67b90edd@-1", "0.f7848bb991fd0be331adcf1457fbc672@0"}; variable 126 {f128, 128},
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZCallingConv.h | 149 if (LocVT == MVT::f128 || LocVT.is128BitVector()) { 156 if (LocVT == MVT::f128) {
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H A D | SystemZISelLowering.cpp | 100 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass); 102 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass); 572 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal); 573 setOperationAction(ISD::FMAXIMUM, MVT::f128, Legal); 574 setOperationAction(ISD::FMINNUM, MVT::f128, Legal); 575 setOperationAction(ISD::FMINIMUM, MVT::f128, Legal); 590 for (auto VT : { MVT::f32, MVT::f64, MVT::f128, 599 // We only have fused f128 multiply-addition on vector registers. 601 setOperationAction(ISD::FMA, MVT::f128, Expand); 602 setOperationAction(ISD::STRICT_FMA, MVT::f128, Expan [all...] |
/netbsd-current/external/lgpl3/mpc/dist/tools/mpcheck/ |
H A D | mpcheck-float128.c | 25 version, and with 'f128' suffix for the __float128 version: 51 #define SUFFIX f128
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64CallingConvention.cpp | 141 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector())
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H A D | AArch64ISelLowering.cpp | 253 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); 415 // Virtually no operation on f128 is legal, but LLVM can't expand them when 417 setOperationAction(ISD::FABS, MVT::f128, Expand); 418 setOperationAction(ISD::FADD, MVT::f128, LibCall); 419 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); 420 setOperationAction(ISD::FCOS, MVT::f128, Expand); 421 setOperationAction(ISD::FDIV, MVT::f128, LibCall); 422 setOperationAction(ISD::FMA, MVT::f128, Expand); 423 setOperationAction(ISD::FMUL, MVT::f128, LibCall); 424 setOperationAction(ISD::FNEG, MVT::f128, Expan [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 466 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal); 470 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal); 1116 addRegisterClass(MVT::f128, &PPC::VRRCRegClass); 1119 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand); 1122 setOperationAction(ISD::SELECT, MVT::f128, Expand); 1124 setTruncStoreAction(MVT::f128, MVT::f64, Expand); 1125 setTruncStoreAction(MVT::f128, MVT::f32, Expand); 1128 setOperationAction(ISD::FSIN, MVT::f128, Expand); 1129 setOperationAction(ISD::FCOS, MVT::f128, Expand); 1130 setOperationAction(ISD::FPOW, MVT::f128, Expan [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Support/ |
H A D | MachineValueType.h | 55 f128 = 13, // This is a 128 bit floating point value 909 case f128: 1106 return MVT::f128;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
H A D | VEISelLowering.cpp | 85 addRegisterClass(MVT::f128, &VE::F128RegClass); 116 setOperationAction(ISD::LOAD, MVT::f128, Custom); 117 setOperationAction(ISD::STORE, MVT::f128, Custom); 227 // VE doesn't have fdiv of f128. 228 setOperationAction(ISD::FDIV, MVT::f128, Expand); 231 // f32 and f64 uses ConstantFP. f128 uses ConstantPool. 497 // TODO: need to calculate offset correctly once we support f128. 1264 // Lower a f128 load into two f64 loads. 1292 DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f128); 1293 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f128, [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 76 case MVT::f128: return "MVT::f128";
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H A D | IntrinsicEmitter.cpp | 276 case MVT::f128: return Sig.push_back(IIT_F128);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 313 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) 324 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; 330 (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128; 336 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; 342 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; 348 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; 354 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; 362 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; 371 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; 374 (VT == MVT::f128) [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 347 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128, 361 setOperationAction(ISD::FREM , MVT::f128 , Expand); 413 setOperationAction(Op, MVT::f128, Expand); 419 setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f16, Expand); 423 setTruncStoreAction(MVT::f128, MVT::f16, Expand); 449 for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) { 727 // f128 uses xmm registers, but most operations require libcalls. 729 addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass 734 setOperationAction(ISD::FADD, MVT::f128, LibCall); 735 setOperationAction(ISD::STRICT_FADD, MVT::f128, LibCal [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 487 RegParmTypes.push_back(MVT::f128);
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