Searched refs:dpte_row_width_ub (Results 1 - 5 of 5) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
H A Damdgpu_display_rq_dlg_calc_20.c396 unsigned int dpte_row_width_ub = 0; local
611 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
613 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
616 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
622 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
624 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
629 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
631 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
667 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
H A Damdgpu_display_rq_dlg_calc_20v2.c396 unsigned int dpte_row_width_ub = 0; local
611 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
613 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
616 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
622 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
624 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
629 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
631 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
667 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
H A Damdgpu_display_rq_dlg_calc_21.c387 unsigned int dpte_row_width_ub = 0; local
612 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
614 dpte_row_width_ub = dml_round_to_multiple(
618 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
624 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
626 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
631 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
633 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
675 (double) dpte_row_width_ub / dpte_group_width,
H A Damdgpu_display_mode_vba_21.c199 unsigned int *dpte_row_width_ub,
1282 unsigned int *dpte_row_width_ub,
1423 *dpte_row_width_ub = (dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
1424 *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
1427 *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
1428 *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
1431 *dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight;
1432 *PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize;
1258 CalculateVMAndRowBytes( struct display_mode_lib *mode_lib, bool DCCEnable, unsigned int BlockHeight256Bytes, unsigned int BlockWidth256Bytes, enum source_format_class SourcePixelFormat, unsigned int SurfaceTiling, unsigned int BytePerPixel, enum scan_direction_class ScanDirection, unsigned int ViewportWidth, unsigned int ViewportHeight, unsigned int SwathWidth, bool GPUVMEnable, bool HostVMEnable, unsigned int HostVMMaxPageTableLevels, unsigned int HostVMCachedPageTableLevels, unsigned int VMMPageSize, unsigned int PTEBufferSizeInRequests, unsigned int Pitch, unsigned int DCCMetaPitch, unsigned int *MacroTileWidth, unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, unsigned int *dpte_row_width_ub, unsigned int *dpte_row_height, unsigned int *MetaRequestWidth, unsigned int *MetaRequestHeight, unsigned int *meta_row_width, unsigned int *meta_row_height, unsigned int *vm_group_bytes, unsigned int *dpte_group_bytes, unsigned int *PixelPTEReqWidth, unsigned int *PixelPTEReqHeight, unsigned int *PTERequestSize, unsigned int *DPDE0BytesFrame, unsigned int *MetaPTEBytesFrame) argument
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
H A Damdgpu_dml1_display_rq_dlg_calc.c601 unsigned int dpte_row_width_ub; local
795 dpte_row_width_ub = 0;
849 * the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
851 dpte_row_width_ub = dml_round_to_multiple(
855 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
860 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
862 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
867 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
869 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
911 (double) dpte_row_width_ub / dpte_group_widt
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