Searched refs:dpte_row_height (Results 1 - 10 of 10) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
H A Damdgpu_display_rq_dlg_calc_20.c203 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
208 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
595 unsigned int dpte_row_height; local
611 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
612 dpte_row_height = 1 << log2_dpte_row_height;
613 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
639 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
1140 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1141 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
H A Damdgpu_display_rq_dlg_calc_20v2.c203 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
208 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
595 unsigned int dpte_row_height; local
611 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
612 dpte_row_height = 1 << log2_dpte_row_height;
613 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
639 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
1141 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1142 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
H A Damdgpu_display_mode_vba_20.c159 unsigned int *dpte_row_height,
218 unsigned int dpte_row_height,
886 unsigned int *dpte_row_height,
1044 *dpte_row_height =
1060 (double) (Pitch * *dpte_row_height - 1)
1064 *dpte_row_height = PixelPTEReqHeight;
1069 *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth);
1896 &mode_lib->vba.dpte_row_height[k],
1975 mode_lib->vba.dpte_row_height[k],
2295 mode_lib->vba.dpte_row_height[
864 CalculateVMAndRowBytes( struct display_mode_lib *mode_lib, bool DCCEnable, unsigned int BlockHeight256Bytes, unsigned int BlockWidth256Bytes, enum source_format_class SourcePixelFormat, unsigned int SurfaceTiling, unsigned int BytePerPixel, enum scan_direction_class ScanDirection, unsigned int ViewportWidth, unsigned int ViewportHeight, unsigned int SwathWidth, bool GPUVMEnable, unsigned int VMMPageSize, unsigned int PTEBufferSizeInRequestsLuma, unsigned int PDEProcessingBufIn64KBReqs, unsigned int Pitch, unsigned int DCCMetaPitch, unsigned int *MacroTileWidth, unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, unsigned int *dpte_row_height, unsigned int *meta_row_height) argument
3088 CalculateFlipSchedule( struct display_mode_lib *mode_lib, double UrgentExtraLatency, double UrgentLatencyPixelDataOnly, unsigned int GPUVMMaxPageTableLevels, bool GPUVMEnable, double BandwidthAvailableForImmediateFlip, unsigned int TotImmediateFlipBytes, enum source_format_class SourcePixelFormat, unsigned int ImmediateFlipBytes, double LineTime, double VRatio, double Tno_bw, double PDEAndMetaPTEBytesFrame, unsigned int MetaRowByte, unsigned int PixelPTEBytesPerRow, bool DCCEnable, unsigned int dpte_row_height, unsigned int meta_row_height, double qual_row_bw, double *DestinationLinesToRequestVMInImmediateFlip, double *DestinationLinesToRequestRowInImmediateFlip, double *final_flip_bw, bool *ImmediateFlipSupportedForPipe) argument
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H A Damdgpu_display_mode_vba_20v2.c183 unsigned int *dpte_row_height,
242 unsigned int dpte_row_height,
946 unsigned int *dpte_row_height,
1104 *dpte_row_height =
1120 (double) (Pitch * *dpte_row_height - 1)
1124 *dpte_row_height = PixelPTEReqHeight;
1129 *dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth);
1932 &mode_lib->vba.dpte_row_height[k],
2011 mode_lib->vba.dpte_row_height[k],
2329 mode_lib->vba.dpte_row_height[
924 CalculateVMAndRowBytes( struct display_mode_lib *mode_lib, bool DCCEnable, unsigned int BlockHeight256Bytes, unsigned int BlockWidth256Bytes, enum source_format_class SourcePixelFormat, unsigned int SurfaceTiling, unsigned int BytePerPixel, enum scan_direction_class ScanDirection, unsigned int ViewportWidth, unsigned int ViewportHeight, unsigned int SwathWidth, bool GPUVMEnable, unsigned int VMMPageSize, unsigned int PTEBufferSizeInRequestsLuma, unsigned int PDEProcessingBufIn64KBReqs, unsigned int Pitch, unsigned int DCCMetaPitch, unsigned int *MacroTileWidth, unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, unsigned int *dpte_row_height, unsigned int *meta_row_height) argument
3125 CalculateFlipSchedule( struct display_mode_lib *mode_lib, double UrgentExtraLatency, double UrgentLatencyPixelDataOnly, unsigned int GPUVMMaxPageTableLevels, bool GPUVMEnable, double BandwidthAvailableForImmediateFlip, unsigned int TotImmediateFlipBytes, enum source_format_class SourcePixelFormat, unsigned int ImmediateFlipBytes, double LineTime, double VRatio, double Tno_bw, double PDEAndMetaPTEBytesFrame, unsigned int MetaRowByte, unsigned int PixelPTEBytesPerRow, bool DCCEnable, unsigned int dpte_row_height, unsigned int meta_row_height, double qual_row_bw, double *DestinationLinesToRequestVMInImmediateFlip, double *DestinationLinesToRequestRowInImmediateFlip, double *final_flip_bw, bool *ImmediateFlipSupportedForPipe) argument
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
H A Damdgpu_display_rq_dlg_calc_21.c182 dml_log2(rq_param.dlg.rq_l.dpte_row_height),
188 dml_log2(rq_param.dlg.rq_c.dpte_row_height),
593 unsigned int dpte_row_height; local
612 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
613 dpte_row_height = 1 << log2_dpte_row_height;
615 data_pitch * dpte_row_height - 1,
641 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
1192 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1193 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
H A Damdgpu_display_mode_vba_21.c200 unsigned int *dpte_row_height,
273 unsigned int dpte_row_height,
438 unsigned int dpte_row_height[],
1283 unsigned int *dpte_row_height,
1418 *dpte_row_height = dml_min(128,
1423 *dpte_row_width_ub = (dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
1426 *dpte_row_height = *PixelPTEReqHeight;
1430 *dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
1964 &locals->dpte_row_height[k],
1994 locals->dpte_row_height[
1258 CalculateVMAndRowBytes( struct display_mode_lib *mode_lib, bool DCCEnable, unsigned int BlockHeight256Bytes, unsigned int BlockWidth256Bytes, enum source_format_class SourcePixelFormat, unsigned int SurfaceTiling, unsigned int BytePerPixel, enum scan_direction_class ScanDirection, unsigned int ViewportWidth, unsigned int ViewportHeight, unsigned int SwathWidth, bool GPUVMEnable, bool HostVMEnable, unsigned int HostVMMaxPageTableLevels, unsigned int HostVMCachedPageTableLevels, unsigned int VMMPageSize, unsigned int PTEBufferSizeInRequests, unsigned int Pitch, unsigned int DCCMetaPitch, unsigned int *MacroTileWidth, unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, unsigned int *dpte_row_width_ub, unsigned int *dpte_row_height, unsigned int *MetaRequestWidth, unsigned int *MetaRequestHeight, unsigned int *meta_row_width, unsigned int *meta_row_height, unsigned int *vm_group_bytes, unsigned int *dpte_group_bytes, unsigned int *PixelPTEReqWidth, unsigned int *PixelPTEReqHeight, unsigned int *PTERequestSize, unsigned int *DPDE0BytesFrame, unsigned int *MetaPTEBytesFrame) argument
3162 CalculateFlipSchedule( struct display_mode_lib *mode_lib, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, double UrgentExtraLatency, double UrgentLatency, unsigned int GPUVMMaxPageTableLevels, bool HostVMEnable, unsigned int HostVMMaxPageTableLevels, unsigned int HostVMCachedPageTableLevels, bool GPUVMEnable, double PDEAndMetaPTEBytesPerFrame, double MetaRowBytes, double DPTEBytesPerRow, double BandwidthAvailableForImmediateFlip, unsigned int TotImmediateFlipBytes, enum source_format_class SourcePixelFormat, double LineTime, double VRatio, double Tno_bw, bool DCCEnable, unsigned int dpte_row_height, unsigned int meta_row_height, unsigned int dpte_row_height_chroma, unsigned int meta_row_height_chroma, double *DestinationLinesToRequestVMInImmediateFlip, double *DestinationLinesToRequestRowInImmediateFlip, double *final_flip_bw, bool *ImmediateFlipSupportedForPipe) argument
5821 CalculateMetaAndPTETimes( unsigned int NumberOfActivePlanes, bool GPUVMEnable, unsigned int MetaChunkSize, unsigned int MinMetaChunkSizeBytes, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], double VRatio[], double VRatioPrefetchY[], double VRatioPrefetchC[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], double BytePerPixelDETY[], double BytePerPixelDETC[], enum scan_direction_class SourceScan[], unsigned int dpte_row_height[], unsigned int dpte_row_height_chroma[], unsigned int meta_row_width[], unsigned int meta_row_height[], unsigned int meta_req_width[], unsigned int meta_req_height[], int dpte_group_bytes[], unsigned int PTERequestSizeY[], unsigned int PTERequestSizeC[], unsigned int PixelPTEReqWidthY[], unsigned int PixelPTEReqHeightY[], unsigned int PixelPTEReqWidthC[], unsigned int PixelPTEReqHeightC[], unsigned int dpte_row_width_luma_ub[], unsigned int dpte_row_width_chroma_ub[], unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], unsigned int meta_pte_bytes_per_frame_ub_l[], unsigned int meta_pte_bytes_per_frame_ub_c[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], double TimePerMetaChunkNominal[], double TimePerMetaChunkVBlank[], double TimePerMetaChunkFlip[], double time_per_pte_group_nom_luma[], double time_per_pte_group_vblank_luma[], double time_per_pte_group_flip_luma[], double time_per_pte_group_nom_chroma[], double time_per_pte_group_vblank_chroma[], double time_per_pte_group_flip_chroma[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], double TimePerVMRequestFlip[]) argument
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
H A Damdgpu_dml1_display_rq_dlg_calc.c602 unsigned int dpte_row_height; local
796 dpte_row_height = 0;
846 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
849 * the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
852 data_pitch * dpte_row_height - 1,
871 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
883 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
938 if (rq_dlg_param->dpte_row_height != func_dpte_row_height) {
940 "MISMATCH: rq_dlg_param->dpte_row_height = %d",
941 rq_dlg_param->dpte_row_height);
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H A Damdgpu_display_rq_dlg_helpers.c93 "DML_RQ_DLG_CALC: dpte_row_height = %0d\n",
94 rq_dlg_param.dpte_row_height);
H A Ddisplay_mode_structs.h387 unsigned int dpte_row_height; member in struct:_vcs_dpi_display_data_rq_dlg_params_st
H A Ddisplay_mode_vba.h586 unsigned int dpte_row_height[DC__NUM_DPP__MAX]; member in struct:vba_vars_st

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