Searched refs:dlg_sys_param (Results 1 - 8 of 8) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/
H A Ddml1_display_rq_dlg_calc.h63 const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
H A Ddisplay_rq_dlg_helpers.h42 void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, display_dlg_sys_params_st dlg_sys_param);
H A Damdgpu_display_rq_dlg_helpers.c141 void print__dlg_sys_params_st(struct display_mode_lib *mode_lib, display_dlg_sys_params_st dlg_sys_param) argument
145 dml_print("DML_RQ_DLG_CALC: t_mclk_wm_us = %3.2f\n", dlg_sys_param.t_mclk_wm_us);
146 dml_print("DML_RQ_DLG_CALC: t_urg_wm_us = %3.2f\n", dlg_sys_param.t_urg_wm_us);
147 dml_print("DML_RQ_DLG_CALC: t_sr_wm_us = %3.2f\n", dlg_sys_param.t_sr_wm_us);
148 dml_print("DML_RQ_DLG_CALC: t_extra_us = %3.2f\n", dlg_sys_param.t_extra_us);
151 dlg_sys_param.t_srx_delay_us);
154 dlg_sys_param.deepsleep_dcfclk_mhz);
157 dlg_sys_param.total_flip_bw);
160 dlg_sys_param.total_flip_bytes);
H A Damdgpu_dml1_display_rq_dlg_calc.c989 const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
1150 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
1152 min_ttu_vblank = dlg_sys_param.t_urg_wm_us;
1154 min_ttu_vblank = dml_max(dlg_sys_param.t_sr_wm_us, min_ttu_vblank);
1156 min_ttu_vblank = dml_max(dlg_sys_param.t_mclk_wm_us, min_ttu_vblank);
1324 (double) dlg_sys_param.t_srx_delay_us);
1398 flip_bw = ((vm_bytes + dpte_row_bytes + meta_row_bytes) * dlg_sys_param.total_flip_bw)
1399 / (double) dlg_sys_param.total_flip_bytes;
1403 dlg_sys_param.t_extra_us,
1413 t_r0_us = dml_max(dlg_sys_param
984 dml1_rq_dlg_get_dlg_params( struct display_mode_lib *mode_lib, struct _vcs_dpi_display_dlg_regs_st *disp_dlg_regs, struct _vcs_dpi_display_ttu_regs_st *disp_ttu_regs, const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param, const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param, const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param, const bool cstate_en, const bool pstate_en, const bool vm_en, const bool iflip_en) argument
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/
H A Damdgpu_display_rq_dlg_calc_20.c58 const display_dlg_sys_params_st dlg_sys_param,
778 const display_dlg_sys_params_st dlg_sys_param,
930 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
1580 display_dlg_sys_params_st dlg_sys_param = {0}; local
1583 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
1584 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib,
1587 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
1588 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
1589 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
1590 dlg_sys_param
771 dml20_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st rq_dlg_param, const display_dlg_sys_params_st dlg_sys_param, const bool cstate_en, const bool pstate_en) argument
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H A Damdgpu_display_rq_dlg_calc_20v2.c58 const display_dlg_sys_params_st dlg_sys_param,
778 const display_dlg_sys_params_st dlg_sys_param,
930 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
1581 display_dlg_sys_params_st dlg_sys_param = {0}; local
1584 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
1585 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib,
1588 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
1589 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
1590 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
1591 dlg_sys_param
771 dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st rq_dlg_param, const display_dlg_sys_params_st dlg_sys_param, const bool cstate_en, const bool pstate_en) argument
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/
H A Damdgpu_display_rq_dlg_calc_21.c824 const display_dlg_sys_params_st dlg_sys_param,
976 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
1681 display_dlg_sys_params_st dlg_sys_param = {0}; local
1684 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
1685 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(
1689 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
1690 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
1691 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
1692 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
1693 dlg_sys_param
816 dml_rq_dlg_get_dlg_params( struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *e2e_pipe_param, const unsigned int num_pipes, const unsigned int pipe_idx, display_dlg_regs_st *disp_dlg_regs, display_ttu_regs_st *disp_ttu_regs, const display_rq_dlg_params_st rq_dlg_param, const display_dlg_sys_params_st dlg_sys_param, const bool cstate_en, const bool pstate_en) argument
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
H A Damdgpu_dcn_calcs.c454 struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0}; local
470 dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
471 if (dlg_sys_param.total_flip_bw < 0.0)
472 dlg_sys_param.total_flip_bw = 0;
474 dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
475 dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
476 dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
477 dlg_sys_param.t_extra_us = v->urgent_extra_latency;
478 dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
479 dlg_sys_param
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