Searched refs:dcfclk_mhz (Results 1 - 8 of 8) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 31 uint32_t dcfclk_mhz; member in struct:gpu_info_voltage_scaling_v1_0
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 55 unsigned int dcfclk_mhz; member in struct:clk_limit_table_entry
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 60 double dcfclk_mhz; member in struct:_vcs_dpi_voltage_scaling_st
352 double dcfclk_mhz; member in struct:_vcs_dpi_display_clocks_and_cfg_st
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| H A D | amdgpu_display_mode_vba.c | 247 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz;
262 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz;
834 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz;
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | amdgpu_rn_clk_mgr.c | 436 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
438 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
519 .dcfclk_mhz = 400,
526 .dcfclk_mhz = 483,
533 .dcfclk_mhz = 602,
540 .dcfclk_mhz = 738,
669 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_resource.c | 236 .dcfclk_mhz = 560.0,
247 .dcfclk_mhz = 694.0,
258 .dcfclk_mhz = 875.0,
269 .dcfclk_mhz = 1000.0,
280 .dcfclk_mhz = 1200.0,
292 .dcfclk_mhz = 1200.0,
2719 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2725 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
[all...] |
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| H A D | amdgpu_dcn21_resource.c | 171 .dcfclk_mhz = 304.0,
182 .dcfclk_mhz = 304.0,
193 .dcfclk_mhz = 608.0,
204 .dcfclk_mhz = 676.0,
215 .dcfclk_mhz = 810.0,
227 .dcfclk_mhz = 810.0,
991 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1352 dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
[all...] |
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| H A D | amdgpu_dcn_calcs.c | 482 input.clks_cfg.dcfclk_mhz = v->dcfclk;
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