| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| H A D | amdgpu_display_rq_dlg_calc_20.c | 327 unsigned int data_pitch,
601 / data_pitch),
611 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
613 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
681 unsigned int data_pitch = 0; local
689 data_pitch = pipe_src_param.data_pitch_c;
694 data_pitch = pipe_src_param.data_pitch;
716 data_pitch,
321 get_meta_and_pte_attr(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st *rq_dlg_param, display_data_rq_misc_params_st *rq_misc_param, display_data_rq_sizing_params_st *rq_sizing_param, unsigned int vp_width, unsigned int vp_height, unsigned int data_pitch, unsigned int meta_pitch, unsigned int source_format, unsigned int tiling, unsigned int macro_tile_size, unsigned int source_scan, unsigned int is_chroma) argument
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| H A D | amdgpu_display_rq_dlg_calc_20v2.c | 327 unsigned int data_pitch,
601 / data_pitch),
611 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
613 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
681 unsigned int data_pitch = 0; local
689 data_pitch = pipe_src_param.data_pitch_c;
694 data_pitch = pipe_src_param.data_pitch;
716 data_pitch,
321 get_meta_and_pte_attr(struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st *rq_dlg_param, display_data_rq_misc_params_st *rq_misc_param, display_data_rq_sizing_params_st *rq_sizing_param, unsigned int vp_width, unsigned int vp_height, unsigned int data_pitch, unsigned int meta_pitch, unsigned int source_format, unsigned int tiling, unsigned int macro_tile_size, unsigned int source_scan, unsigned int is_chroma) argument
|
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| H A D | amdgpu_display_rq_dlg_calc_21.c | 314 unsigned int data_pitch,
602 / data_pitch),
612 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
615 data_pitch * dpte_row_height - 1,
690 unsigned int data_pitch = 0; local
698 data_pitch = pipe_param.src.data_pitch_c;
703 data_pitch = pipe_param.src.data_pitch;
756 data_pitch,
307 get_meta_and_pte_attr( struct display_mode_lib *mode_lib, display_data_rq_dlg_params_st *rq_dlg_param, display_data_rq_misc_params_st *rq_misc_param, display_data_rq_sizing_params_st *rq_sizing_param, unsigned int vp_width, unsigned int vp_height, unsigned int data_pitch, unsigned int meta_pitch, unsigned int source_format, unsigned int tiling, unsigned int macro_tile_size, unsigned int source_scan, unsigned int hostvm_enable, unsigned int is_chroma) argument
|
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| H A D | amdgpu_dml1_display_rq_dlg_calc.c | 374 unsigned int data_pitch,
510 dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch),
552 unsigned int data_pitch = 0; local
614 data_pitch = pipe_src_param.data_pitch_c;
619 data_pitch = pipe_src_param.data_pitch;
837 dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch),
849 * the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
852 data_pitch * dpte_row_height - 1,
919 data_pitch,
369 dml1_rq_dlg_get_row_heights( struct display_mode_lib *mode_lib, unsigned int *o_dpte_row_height, unsigned int *o_meta_row_height, unsigned int vp_width, unsigned int data_pitch, int source_format, int tiling, int macro_tile_size, int source_scan, int is_chroma) argument
[all...] |
| H A D | display_mode_structs.h | 242 unsigned int data_pitch; member in struct:_vcs_dpi_display_pipe_source_params_st
|
| H A D | amdgpu_display_mode_vba.c | 403 mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch;
|
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_resource.c | 2083 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
2121 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2126 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
|
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| H A D | amdgpu_dcn_calcs.c | 340 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width;
|