Searched refs:WR5_DTR (Results 1 - 4 of 4) sorted by relevance

/netbsd-current/sys/arch/luna68k/dev/
H A Dsioreg.h142 #define WR5_DTR 0x80 /* Data Terminal Ready [DTR] */ macro
H A Dsiotty.c69 WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS, /* Tx */
471 val |= WR5_DTR;
478 wr5 &= ~(WR5_BREAK|WR5_DTR|WR5_RTS);
489 if ((wr5 & WR5_DTR) != 0)
/netbsd-current/sys/arch/luna68k/stand/boot/
H A Dsioreg.h160 #define WR5_DTR 0x80 /* Data Terminal Ready [DTR] */ macro
H A Dsio.c230 sioreg(REG(0, WR5), WR5_TX8BIT | WR5_TXENBL | WR5_DTR | WR5_RTS);

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